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BMA255

Data sheet

Page 25

BST-BMA255-DS004-05 | Revision 1.2 | August 2014

Bosch Sensortec

third parties. BOSCH and the symbol are registered trademarks of Robert Bosch GmbH, Germany.

Note: Specifications within this document are subject to change without notice.

4.6 Non-volatile memory

The entire memory of the BMA255 consists of three different kinds of registers: hard-wired,

volatile, and non-volatile. Part of it can be both read and written by the user. Access to non-

volatile memory is only possible through (volatile) image registers.

Altogether, there are eight registers (octets) with NVM backup which are accessible by the user.

The addresses of the image registers range from 0x38 to 0x3C. While the addresses up to

0x3A are used for offset compensation (see 4.4 Offset Compensation), addresses 0x3B and

0x3C are general purpose registers not linked to any sensor-specific functionality.

The content of the NVM is loaded to the image registers after a reset (either POR or softreset)

or after a user request which is performed by writing ´1´ to the write-only bit (0x33) nvm_load.

As long as the image update is in progress, bit (0x33) nvm_rdy is ´0´, otherwise it is ´1´.

The image registers can be read and written like any other register.

Writing to the NVM is a three-step procedure:

1. Write the new contents to the image registers.

2. Write ´1´ to bit (0x33) nvm_prog_mode in order to unlock the NVM.

3. Write ´1´ to bit (0x33) nvm_prog_trig and keep ´1´ in bit (0x33) nvm_prog_mode in order

to trigger the write process.

Writing to the NVM always renews the entire NVM contents. It is possible to check the write

status by reading bit (0x33) nvm_rdy. While (0x33) nvm_rdy = ´0´, the write process is still in

progress; if (0x33) nvm_rdy = ´1´, then writing is completed. As long as the write process is

ongoing, no change of power mode and image registers is allowed. Also, the NVM write cycle

must not be initiated while image registers are updated, in low-power mode, and in suspend

mode.

Please note that the number of permitted NVM write-cycles is limited as specified in Table 1.

The number of remaining write-cycles can be obtained by reading bits (0x33) nvm_remain.

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