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GS3470 Datasheet(PDF) 125 Page - Semtech Corporation |
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GS3470 Datasheet(HTML) 125 Page - Semtech Corporation |
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125 / 169 page ![]() GS3470 Final Data Sheet Rev.8 PDS-060500 September 2017 125 of 169 Semtech www.semtech.com 86D OFFSET_ CORRECTION_ CFG RSVD 15:7 — — Reserved. IB_PD_OFFSET_PATH_1 6:6 RW 0 Powers down the offset DACs for input 1. Shuts off all offset correction from that input. IB_PD_OFFSET_PATH_0 5:5 RW 0 Powers down the offset DACs for input 0. Shuts off all offset correction from that input. RSVD 4:0 RW 0 Reserved. 86E RSVD RSVD 15:0 — — Reserved. 86F LOS_CTRL RSVD 15:9 — — Reserved. LOS_AFE_SEL 8:8 RW 1 AFE select: 0 = Selects DDI0 (directly from pin) for LOS sensing 1 = Selects DDI1 (directly from pin) for LOS sensing LOS_CD_TIME_ CONSTANT 7:6 RW 1 Time constant. LOS_CD_HYSTERESIS 5:4 RW 1 LOS hysteresis. RSVD 3:0 RW 5 Reserved. 870 DELAY_LINE_ CTRL_1 RSVD 15:15 — — Reserved. PCLK_DELAY_SD 14:10 RW 0 Controls the offset for the delay line in SD: 00000b = No delay 11111b = Max delay Step Size = 0.006 UI PCLK_DELAY_HD 9:5 RW 0 Controls the offset for the delay line in HD: 00000b = No delay 11111b = Max delay Step Size = 0.031 UI PCLK_DELAY_3G 4:0 RW 0 Controls the offset for the delay line in 3G: 00000b = No delay 11111b = Max delay Step Size = 0.031 UI 871 DELAY_LINE_ CTRL_2 RSVD 15:3 — — Reserved. PCLK_INVERT_SD 2:2 RW 0 Controls the inversion of PCLK in SD. PCLK_INVERT_HD 1:1 RW 0 Controls the inversion of PCLK in HD. PCLK_INVERT_3G 0:0 RW 0 Controls the inversion of PCLK in 3G. 872 to 873 RSVD RSVD 15:0 — — Reserved. Table 5-8: Video Core CSR Descriptions (Continued) Addressh Register Name Parameter Name Bit Slice R/W Reset Valueh Description |
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