GS3470 datasheet(126/169 Pages) SEMTECH

126 / 169 page

GS3470

Final Data Sheet

Rev.8

PDS-060500

September 2017

126 of 169

Semtech

www.semtech.com

874

CLK_GEN

RSVD

15:3

—

Reserved.

DDR_PHASE_

DET_INVERT

2:2

Swaps the phase in DDR mode.

User can choose whether to start data

transmission from a rising edge or a falling

edge of the DDR clock.

RSVD

1:1

Reserved.

SD_HD_DDR_SEL

0:0

Enables DDR mode for SD, HD, and

non-SMPTE data if DDR is supported for

that specific rate.

875

PD_CTRL

RSVD

15:12

—

Reserved.

POL_INV

11:11

Phase Detector Polarity Invert:



0 = PD uses normal data polarity



1 = PD uses inverted data polarity

RSVD

10:0

—

Reserved.

876

RSVD

15:0

—

Reserved.

877

PIN_CSR_

SELECT

RSVD

15:3

—

Reserved.

20BIT_10BIT

2:2

CSR value for 20BIT_10BIT to be used

when 20BIT_10BIT_PIN = 1



0 = Output parallel data bus is 10 bits

1 = Output parallel data bus is 20 bits

20BIT_10BIT_PIN

1:1

Override for 20BIT_10BIT pin:



0 = Selects pin value



1 = Selects CSR value

IOPROC_EN

0:0

CSR value for IOPROC_EN:



0 = Disables all video and audio

processing



1 = Enables all video and audio processing

that are not masked in the IOPROC_1,

IOPROC_2 registers

Table 5-8: Video Core CSR Descriptions (Continued)

Addressh

Parameter Name

Bit

Slice

R/W

Reset

Valueh

Description

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