AD5753 datasheet(32/72 Pages) AD

32 / 72 page

AD5753

Data Sheet

Rev. 0 | Page 32 of 72

Transfer Function

Table 8 shows the input code to ideal output voltage relationship for

the AD5753 for straight binary data coding of the ±5 V output

range.

Table 8. Ideal Output Voltage to Input Code Relationship

Digital Input, Straight Binary

Data Coding

Analog Output

MSB

LSB

VOUT

1111

2 × VREF × (32,767/32,768)

1111

1110

2 × VREF × (32,766/32,768)

1000

0000

0 V

0000

0001

−2 × VREF × (32,767/32,768)

0000

−2 × VREF

POWER-ON STATE OF THE AD5753

On initial power-on or a device reset, the voltage and current

output channel is disabled. The switch connecting the VIOUT via a

30 kΩ pull-down resistor to AGND is open. This switch can be

configured in the DCDC_CONFIG2 register. VDPC+ and VDPC−

are internally driven to ±4.8 V upon power-on, until the dc-to-

dc converters are enabled.

After device power-on or a device reset, a calibration memory

refresh command is required (see the Programming Sequence

to Enable the Output section). It is recommended to wait 500 μs

at minimum after writing this command before writing further

instructions to the device to allow time for internal calibrations

to take place.

Power-On Reset

3.3V

VLDO

POWER-ON

RESET

SOFTWARE

RESET

HARDWARE

RESET

INT_AVCC

RESET

SDI

SCLK

VLDO

AVDD2

SYNC

Figure 76. Power-On Reset Block Diagram

The AD5753 incorporates a power-on reset circuit that ensures the

AD5753 is held in reset if the power supplies are insufficient

enough to allow reliable operation. The power-on reset circuit

(see Figure 76) monitors the AVDD2 generated VLDO, the INT_

AVCC voltages, the RESET pin, and the SPI reset signal. The

power-on reset circuit keeps the AD5753 in reset until the voltages

on the VLDO and an internal AVCC voltage node (INT_AVCC) are

sufficient for reliable operation. The AD5753 is reset if the

power-on circuit receives a signal from the RESET pin or if a

software reset is written to the AD5753 via the SPI interface. Do

not write SPI commands to the device within 100 μs of a reset

event.

POWER SUPPLY CONSIDERATIONS

The AD5753 has the following four supply rails: AVDD1, AVDD2,

AVSS, and VLOGIC. See Table 1 for the voltage range of the four

supply rails and the associated conditions.

AVDD1 Considerations

AVDD1 is the supply rail for the positive dc-to-dc converter and can

range from 7 V to 33 V. Although the maximum value of AVDD1 is

33 V and the minimum value of AVSS is −33 V, the maximum

operating range of |AVDD1 to AVSS| is 60 V. VDPC+ is derived from

AVDD1 and the value depends on the dc-to-dc converter mode of

operation

The dc-to-dc converter requires a sufficient level of margin to be

maintained between AVDD1 and VDPC+ to ensure the dc-to-dc

circuitry operates correctly. This margin is 5% of the maximum

VDPC+ voltage for a given mode of operation.

Table 9. AVDD1 to VDPC+ Margin

Mode of Operation

VDPC+ Maximum

DPC Voltage Mode

15 V

DPC Current Mode

(IOUT maximum × RLOAD) + IOUT headroom

PPC Current Mode

DCDC_CONFIG1[4:0] programmed value

See the Power Dissipation Control section for further details on

the dc-to-dc converter modes of operation.

Calculating Supply Voltage

Assuming DPC current mode, use the following equation to

calculate the supply voltage:

VDPC+ maximum = IOUT maximum voltage + IOUT headroom

= 22.5 V

where:

IOUT maximum = 20 mA; RLOAD = 1 kΩ

IOUT maximum voltage = IOUT maximum × RLOAD = 20 V

IOUT headroom = 2.5 V

|VDPC+ to AVDD1| headroom is calculated as 5% of 22.5 V =

1.125 V. Therefore, AVDD1 (minimum) = 22.5 V + 1.125 V =

23.625 V. Assuming a worst case AVDD1 supply rail tolerance of

±10%, this example requires an AVDD1 supply rail of

approximately 26 V.

AVSS Considerations

AVSS is the negative supply rail and has a range of −33 V to 0 V. As

in the case of AVDD1, AVSS must obey the 60 V maximum operating

range of |AVDD1 to AVSS|. VDPC− is derived from AVSS and the value

depends on the dc-to-dc converter mode of operation. The dc-

to-dc converter requires a sufficient level of margin between

AVSS and VDPC− to ensure the dc-to-dc circuitry operates

correctly. This margin is 5% of the maximum |VDPC−| voltage for

a given mode of operation.

AD5753 Datasheet(PDF) 32 Page - Analog Devices

AD5753 Datasheet(HTML) 32 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72

Datasheet Download

Link URL