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AD5753 Datasheet(PDF) 62 Page - Analog Devices

Part # AD5753
Description  Single-Channel, 16-Bit Current and Voltage DAC
PDF  72 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD5753 Datasheet(HTML) 62 Page - Analog Devices

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AD5753
Data Sheet
Rev. 0 | Page 62 of 72
GPIO Data Register
Address: 0x0E, Reset: 0x0E0000, Name: GPIO_DATA
The GPIO_DATA register is used to read and write from and to the GPIO_0, GPIO_1, and GPIO_2 pins.
Table 41. Bit Descriptions for GPIO_DATA
Bits
Bit Name
Description
Reset
Access
21
FAULT_PIN_STATUS
The FAULT_PIN_STATUS bit reflects the current status of the FAULT pin.
0x0
R
[20:16]
REGISTER_ADDRESS
Register address.
0x0
R
[15:6]
Reserved
Reserved.
0x0
R0
5
GPI_2_READ
User readable bit. This bit reflects the logic value on the GPIO_2 pin in GPO and GPI
mode.
0x0
R
4
GPO_2_WRITE
User writable bit. This bit reflects the GPIO_2 pin logic value in GPO mode.
0x0
R/W
3
GPI_1_READ
User readable bit. This bit reflects the logic value on the GPIO_1 pin in GPO and GPI
mode.
0x0
R
2
GPO_1_WRITE
User writable bit. This bit reflects the GPIO_1 pin logic value in GPO mode.
0x0
R/W
1
GPI_0_READ
User readable bit. This bit reflects the logic value on the GPIO_0 pin in GPO and GPI
mode.
0x0
R
0
GPO_0_WRITE
User writable bit. This bit reflects the GPIO_0 pin logic value in GPO mode.
0x0
R/W
WDT Configuration Register
Address: 0x0F, Reset: 0x0F0009, Name: WDT_CONFIG
The WDT_CONFIG register configures the WDT timeout values. This register also configures the acceptable resets for WDT setup and
configures the resulting response to a WDT fault, for example, clears the output or resets the device.
Table 42. Bit Descriptions for WDT_CONFIG
Bits
Bit Name
Description
Reset
Access
21
FAULT_PIN_STATUS
The FAULT_PIN_STATUS bit reflects the inverted current status of the FAULT pin.
0x0
R
[20:16]
REGISTER_ADDRESS
Register address.
0x0
R
[15:11]
Reserved
Reserved. Do not alter the default value of these bits.
0x0
R
10
CLEAR_ON_WDT_FAIL
Enable clear on WDT fault. If the WDT times out, a clear event occurs, whereby the
output is loaded with the clear code stored in the CLEAR_CODE register.
0x0
R/W
0: disable (default).
1: enable.
9
RESET_ON_WDT_FAIL
Enables a software reset to automatically occur if the WDT times out.
0x0
R/W
0: disable (default).
1: enable.
8
KICK_ON_VALID_WRITE
Enables any valid SPI command to reset the WDT. Any active WDT error flags must
be cleared before the WDT can be restarted.
0x0
R/W
0: disable (default).
1: enable.
7
Reserved
Reserved. Do not alter the default value of this bit.
0x0
R/W
6
WDT_EN
Enables the WDT, then starts the WDT, assuming there are no active WDT fault flags.
0x0
R/W
0: disable (default).
1: enable.
[5:4]
Reserved
Reserved. Do not alter the default value of these bits.
0x0
R/W
[3:0]
WDT_TIMEOUT
Sets the WDT timeout value. Setting WDT_TIMEOUT to a binary value beyond
0b1010 results in the default setting of 1 sec.
0x9
R/W
0000: 1 ms.
0001: 5 ms.
0010: 10 ms.
0011: 25 ms.
0100: 50 ms.
0101: 100 ms.
0110: 250 ms.



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