AD5753 datasheet(11/72 Pages) AD

11 / 72 page

Data Sheet

AD5753

Rev. 0 | Page 11 of 72

TIMING CHARACTERISTICS

AVDD1 = VDPC+ = 15 V, dc-to-dc converter disabled, AVDD2 = 5 V, AVSS = VDPC− = −15 V, VLOGIC = 1.71 V to 5.5 V, AGND = DGND =

REFGND = PGND1 = 0 V, REFIN = 2.5 V external, voltage output: RLOAD = 1 kΩ, CLOAD = 220 pF, current output: RLOAD = 300 Ω. All

specifications at TA = −40°C to +115°C, TJ < 125°C, unless otherwise noted. The units indicate the minimum or maximum time the

action takes to complete.

Table 3.

Parameter1, 2, 3

1.71 V ≤ VLOGIC < 3 V

3 V ≤ VLOGIC ≤ 5.5 V

Unit

Description

ns minimum

Serial clock input (SCLK) cycle time, write operation

120

ns minimum

SCLK cycle time, read operation

ns minimum

SCLK high time, write operation

ns minimum

SCLK high time, read operation

ns minimum

SCLK low time, write operation

ns minimum

SCLK low time, read operation

ns minimum

SYNC falling edge to SCLK falling edge setup time,

write operation

ns minimum

SYNC falling edge to SCLK falling edge setup time,

read operation

ns minimum

24th or 32nd SCLK falling edge to SYNC rising edge

500

ns minimum

SYNC high time (applies to all register writes outside

of those listed in this table)

1.5

µs minimum

SYNC high time (DAC_INPUT register write)

500

µs minimum

SYNC high time (DAC_CONFIG register write, where

the Range[3:0] bits change; see the Calibration

Memory CRC section for more timing information

ns minimum

Data setup time

ns minimum

Data hold time

750

ns minimum

LDAC falling edge to SYNC rising edge

t10

1.5

µs minimum

SYNC rising edge to LDAC falling edge

t11

250

ns minimum

LDAC pulse width low

t12

600

ns maximum

LDAC falling edge to DAC output response time,

digital slew rate control disabled.

µs maximum

LDAC falling edge to DAC output response time,

digital slew rate control enabled.

t13

See the AC Performance

Characteristics section

See the AC Performance

Characteristics section

µs maximum

DAC output settling time

t14

1.5

µs maximum

SYNC rising edge to DAC output response time

(LDAC = 0)

t15

µs minimum

RESET pulse width

t16

ns maximum

SCLK rising edge to SDO valid

t17

100

µs minimum

RESET rising edge to first SCLK falling edge after

SYNC falling edge (t17 does not appear in the timing

diagrams)

Guaranteed by design and characterization; not production tested.

All input signals are specified with tR = tF = 5 ns (10% to 90% of VLOGIC) and timed from a voltage level of 1.2 V. tR is rise time. tF is fall time.

See Figure 2, Figure 3, Figure 4, and Figure 5.

AD5753 Datasheet(PDF) 11 Page - Analog Devices

AD5753 Datasheet(HTML) 11 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72

Datasheet Download

Link URL