| Electronic Components Datasheet Search |
|
AD5753 Datasheet(PDF) 40 Page - Analog Devices |
|
|
|||||||||||||||||||||||||||||
AD5753 Datasheet(HTML) 40 Page - Analog Devices |
|
40 / 72 page ![]() AD5753 Data Sheet Rev. 0 | Page 40 of 72 The decimal value that is written to the internal DAC register (DAC code) is calculated with the following equation: 15 16 ( 1) 2 2 M DAC code D C + = × +− where: D is the code loaded to the DAC_INPUT register. M is the code in the USER_GAIN register (default code = 216 − 1). C is the code in the USER_OFFSET register (default code = 215). Data from the DAC_INPUT register is processed by a digital multiplier and adder and both are controlled by the contents of the user gain and user offset registers, respectively. The calibrated DAC data is then loaded to the DAC. The loading of the DAC data is dependent on the state of the LDAC pin. Each time data is written to the USER_GAIN or USER_ OFFSET register, the DAC output is not automatically updated. Instead, the next write to the DAC_INPUT register uses these user gain and user offset values to perform a new calibration and to automatically update the output channel. The read only DAC_OUTPUT register represents the value currently available at the DAC output, except in the case of user gain and user offset calibration. In this case, the DAC_OUTPUT register contains the DAC data input by the user, on which the calibration is performed and not the result of the calibration. Both the USER_GAIN register and the USER_OFFSET register have 16 bits of resolution. The correct method to calibrate the gain and offset is to first calibrate the gain and then calibrate the offset. DAC OUTPUT UPDATE AND DATA INTEGRITY DIAGNOSTICS Figure 83 shows a simplified version of the DAC input loading circuitry. If used, the USER_GAIN and USER_OFFSET registers must be updated before writing to the DAC_INPUT register. VIOUT INTERFACE LOGIC OUTPUT AMPLIFIER SDO SDI 16-BIT DAC REFIN SYNC LDAC (HARDWARE OR SOFTWARE) DAC INPUT REGISTER USER GAIN AND OFFSET CALIBRATION SCLK DAC OUTPUT REGISTER (READ ONLY) CLEAR CODE REGISTER CLEAR EVENT (WDT TIMEOUT) Figure 83. Simplified Serial Interface of Input Loading Circuitry |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |