AD5753 datasheet(65/72 Pages) AD

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Data Sheet

AD5753

Rev. 0 | Page 65 of 72

FAULT Pin Configuration Register

Address: 0x12, Reset: 0x120000, Name: FAULT_PIN_CONFIG

The FAULT register masks particular fault bits from the FAULT pin, if so desired.

Table 45. Bit Descriptions for FAULT_PIN_CONFIG

Bits

Bit Name

Description

Reset

Access

FAULT_PIN_STATUS

The FAULT_PIN_STATUS bit reflects the inverted current status of the FAULT pin.

0x0

[20:16]

REGISTER_ADDRESS

0x0

INVALID_SPI_ACCESS_ERR

If this bit is set, do not map the INVALID_SPI_ACCESS_ERR fault flag to the FAULT pin.

0x0

R/W

VIOUT_OV_ERR

If this bit is set, do not map the VIOUT_OV_ERR fault flag to the FAULT pin.

0x0

R/W

Reserved

Reserved. Do not alter the default value of this bit.

0x0

R/W

INVERSE_DAC_CHECK_ERR

If this bit is set, do not map the INVERSE_DAC_CHECK_ERR flag to the FAULT pin.

0x0

R/W

Reserved

Reserved. Do not alter the default value of this bit.

0x0

R/W

OSCILLATOR_STOP_DETECT

If this bit is set, do not map the clock stop error to the FAULT pin.

0x0

R/W

DAC_LATCH_MON_ERR

If this bit is set, do not map the DAC_LATCH_MON_ERR fault flag to the FAULT pin.

0x0

R/W

WDT_ERR

If this bit is set, do not map the WDT_ERR flag to the FAULT pin.

0x0

R/W

SLIPBIT_ERR

If this bit is set, do not map the SLIPBIT_ERR error flag to the FAULT pin.

0x0

R/W

SPI_CRC_ERR

If this bit is set, do not map the SPI_CRC_ERR error flag to the pin.

0x0

R/W

Reserved

Reserved. Do not alter the default value of this bit.

0x0

R/W

DCDC_P_SC_ERR

If this bit is set, do not map the positive rail dc-to-dc short circuit error flag to the

FAULT pin.

0x0

R/W

IOUT_OC_ERR

If this bit is set, do not map the current output open-circuit error flag to the FAULT pin.

0x0

R/W

VOUT_SC_ERR

If this bit is set, do not map the voltage output short-circuit error flag to the FAULT pin.

0x0

R/W

DCDC-DIE_TEMP_ERR

If this bit is set, do not map the dc-to-dc die temperature error flag to the FAULT pin.

0x0

R/W

MAIN_DIE_TEMP_ERR

If this bit is set, do not map the main die temperature error flag to the FAULT pin.

0x0

R/W

Two-Stage Readback Select Register

Address: 0x13, Reset: 0x130000, Name: TWO_STAGE_READBACK_SELECT

The TWO_STAGE_READBACK_SELECT register selects the address of the register required for a two-stage readback operation. The

address of the register selected for readback is stored in Bits[D4:D0].

Table 46. Bit Descriptions for TWO_STAGE_READBACK_SELECT

Bits

Bit Name

Description

Reset

Access

FAULT_PIN_STATUS

The FAULT_PIN_STATUS bit reflects the inverted current status of the FAULT pin.

0x0

[20:16]

REGISTER_ADDRESS

0x0

[15:7]

Reserved

Reserved.

0x0

[6:5]

READBACK_MODE

These bits control the SPI readback mode.

0x0

R/W

0: two-stage SPI readback mode (default).

01: autostatus readback mode. The status register contents are shifted out on SDO for

every SPI frame.

10: shared SYNC autostatus readback mode. This mode allows the use of a shared SYNC

line on multiple devices (distinguished using the hardware address pins). After each valid

write to a device, a flag is set. This mode behaves similar to the normal autostatus readback

mode, except that the device does not output the status register contents on SDO as

SYNC goes low, unless the internal flag is set (previous SPI write is valid).

11: the status register contents and the previous SPI frame instruction are alternately

available on SDO.

[4:0]

READBACK_SELECT

Selects readback address for a two-stage readback.

0x0

R/W

0x00: NOP register (default).

0x01: DAC_INPUT register.

0x02: DAC_OUTPUT register.

0x03: CLEAR_CODE register.

0x04: USER_GAIN register.

AD5753 Datasheet(PDF) 65 Page - Analog Devices

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