AD5753 datasheet(39/72 Pages) AD

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Data Sheet

AD5753

Rev. 0 | Page 39 of 72

The two-stage readback consists of a write to a dedicated

operation (NOP) command during which the contents of the

selected register are available on the SDO pin.

Table 13. SDO Contents for Read Operation

MSB

LSB

[D31:D30] D29

[D28:24]

[D23:D8] [D7:D0]

0b10

FAULT pin status Register address

Data

CRC

Bits[D31:D30] = 0b10 are used for synchronization purposes

during readback.

If autostatus readback mode is selected, the contents of the status

This feature allows the user to continuously monitor the status

with this feature disabled. When this feature is enabled, the

normal two-stage readback feature is not available. Only the

status register is available on SDO. To read back other registers,

first disable the automatic readback feature before following the

two-stage readback sequence. The automatic status readback

can be reenabled after the register is read back.

The shared AD5753 SYNC autostatus readback is a special

version of the autostatus readback mode used to avoid SDO bus

contention when multiple devices share the same SYNC line.

Echo mode behaves similarly to autostatus readback mode,

except that every second readback consists of an echo (a

repetition) of the previous command written to the AD5753

(see Figure 82). See the Reading from Registers section for

further details on the readback modes.

COMMAND

STATUS

CONTENTS

COMMAND

Figure 82. SDO Contents, Echo Mode

WDT

The WDT feature ensures that communication is not lost between

the system controller and the AD5753, and that the SPI

datapath lines function as expected.

When enabled, the WDT alerts the system if the AD5753 has not

received a specific SPI frame in the user programmable timeout

period. When the specific SPI frame is received, the watchdog

resets the timer controlling the timeout alert. The SPI frame

used to reset the WDT is configurable as one of the two

following choices:



A specific key code write to the key register (default).



A valid SPI write to any register.

When a watchdog timeout event occurs, there are two user

configurable actions the AD5753 takes. The first is to load the

DAC output with a user defined clear code stored in the

CLEAR_CODE register. The second is to perform a software

reset. These two actions can be enabled via Bit 10 and Bit 9,

respectively, in the WDT_CONFIG register. On a watchdog

timeout event, regardless if Bit 10 or Bit 9 is enabled, a dedicated

WDT_STATUS bit in the status register, as well as a WDT_ERR bit

in the DIGITAL_DIAG_RESULTS register, alerts the user that the

WDT is timed out. After a WDT timeout occurs, all writes to the

DAC_INPUT register, as well as the hardware or software LDAC

events, are ignored until the active WDT fault flag within the

DIGITAL_DIAG_RESULTS register clears.

After the active WDT fault flag clears, the WDT restarts by

performing a subsequent WDT reset command.

On power-up, the WDT is disabled by default. The default

timeout setting is 1 sec. The default method to reset the WDT is

to write one specific key. On timeout, the default action is to set

the relevant WDT_ERR flag bits and the FAULT pin. See Table 42

for the specific register bit details to support the configurability of

the WDT operation.

USER DIGITAL OFFSET AND GAIN CONTROL

The AD5753 has a USER_GAIN register and a USER_OFFSET

chain. The 16-bit USER_GAIN register allows the user to adjust the

gain of the DAC channel in steps of 1 LSB. The USER_GAIN

code in the USER_GAIN register is 0xFFFF, which results in a no

gain factor applied to the programmed output. In theory, the gain

can be tuned across the full range of the output. In practice, the

maximum recommended gain trim is approximately 50% of the

programmed range to maintain accuracy.

Table 14. Gain Register Adjustment

Gain Adjustment Factor

D15

[D14:D1]

65,535/65,536

…

2/65,536

1/65,536

The 16-bit USER_OFFSET register allows the user to adjust the

offset of the DAC channel from −32,768 LSBs to +32,768 LSBs

in steps of 1 LSB. The USER_OFFSET register coding is straight

binary, as shown in Table 15. The default code in the USER_

OFFSET register is 0x8000, which results in zero offset

programmed to the output.

Table 15. Offset Register Adjustment

Gain Adjustment

D15

[D13:D2]

+32,768 LSBs

+32,767 LSBs

…

No Adjustment (Default)

…

−32,767 LSBs

−32,768 LSBs

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