AD5753 datasheet(8/72 Pages) AD

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AD5753

Data Sheet

Rev. 0 | Page 8 of 72

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

ADC

Resolution

Bits

Input Voltage Range

ADC1 Pin

0.5

ADC_IP_SELECT = 10000

−0.5

+0.5

ADC_IP_SELECT = 10010, AVSS must be ≤ −1 V

1.25

ADC_IP_SELECT = 01111

2.5

ADC_IP_SELECT = 10001

ADC2 Pin

−15

+15

Total Error

ADC1 Pin

−0.25

+0.25

% FSR

2.5 V input range

−0.3

+0.3

% FSR

1.25 V input range

−0.5

+0.5

% FSR

0 V to 0.5 V and ±0.5 V input ranges

ADC2 Pin

−0.5

+0.5

% FSR

All other ADC Inputs

±0.3

% FSR

Table 18 lists all ADC input nodes

Conversion Time2

100

μs

GENERAL-PURPOSE

INPUT/OUTPUT OUTPUT

ISOURCE or ISINK5

VLOGIC/1 kΩ

Assume 1 kΩ is connected to the GPIO pin

Output Voltage

Low, VOL

0.4

ISOURCE = 2 mA

High, VOH

VLOGIC − 0.2

ISOURCE = 2 mA

GPIO INPUT

Input Voltage

High, VIH

0.7 × VLOGIC

Low, VIL

0.3 × VLOGIC

Input Current

1.35

μA

Input Capacitance

2.6

DIGITAL OUTPUTS

SDO

Output Voltage

Low, VOL

0.4

Sinking = 200 μA

High, VOH

VLOGIC − 0.2

Sourcing = 200 μA

High Impedance Leakage

Current

−1

μA

High Impedance Output

Capacitance2

2.2

FAULT

Output Voltage

Low, VOL

0.4

10 kΩ pull-up resistor to VLOGIC

0.6

At 2.5 mA

High, VOH

VLOGIC −

0.05

10 kΩ pull-up resistor to VLOGIC

DIGITAL INPUTS

Input Voltage

3 V ≤ VLOGIC ≤ 5.5 V

High, VIH

0.7 × VLOGIC

Low, VIL

0.3 × VLOGIC

1.71 V ≤ VLOGIC < 3 V

High, VIH

0.8 × VLOGIC

Low, VIL

0.2 × VLOGIC

Input Current

−1.5

+1.5

μA

Per pin, internal pull-down on SCLK, SDI, RESET,

and LDAC; internal pull-up on SYNC

Pin Capacitance2

2.4

Per pin

AD5753 Datasheet(PDF) 8 Page - Analog Devices

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