9880 datasheet(30/118 Pages) INTEL

30 / 118 page

LXT9860/9880 — Advanced 10/100 Repeater with Integrated Management

Datasheet

Document #: 248987

Revision#: 003

Rev Date: 08/07/01

Table 11. Miscellaneous Signal Descriptions

Symbol

Type

1, 2

Description

RESET

Schmitt

Reset. This active Low input causes internal circuits, state

machines and counters to reset (address tracking registers do not

reset). On power-up, devices should not be brought out of reset

until the power supply stabilizes to 3.3V. When there are multiple

devices, it is recommended all be supplied by a common reset

driven by an ‘LS14 or similar device.

CLK25

Schmitt

25 MHz system clock. Refer to Table 29 on page 75 for clock

requirements.

CHIPID0

CHIPID1

Chip ID. These pins assign unique Chip IDs to as many as four

devices on a single board. One device on each board must be

assigned ChipID = 00. See “Serial Management I/F” on page 52.

CONFIG(0) /

CFG_DT

Configuration Register Input 0. The CONFIG[1:0] inputs allow

the user to store system-specific information (board type, plug-in

cards, status, etc.) in the Serial Configuration Register (hex

address AC). This register may be read remotely through the

Serial Management Interface (SMI).

Configuration Bus Data. Used in conjunction with CFG_CLK

and CFG_LD, these pins provide an expansion capability for the

functionality of CONFIG[1:0]. Using an external Parallel-to-Serial

device, up to 8 Configuration inputs can be brought to the SMI for

user access.

The Configuration Mode Select bit (Bit 14) in the Repeater

Configuration Register is used to choose between CONFIG[1:0]

and CFG bus modes. (See Table 75 on page 109.)

CONFIG(1) /

CFG_LD

I/O

Configuration Register Input 1. The CONFIG[1:0] inputs allow

the user to store system-specific information (board type, plug-in

cards, status, etc.) in the Repeater Serial Configuration register.

This register may be read remotely through the Serial

Management Interface (SMI).

Configuration Bus Load (active Low). Used in conjunction with

CFG_CLK and CFG_DT, this active Low pin provides an

expansion capability for the functionality of CONFIG[1:0]. Using

an external Parallel-to-Serial device, up to 8 Config. inputs can be

brought to the SMI for user access.

The Configuration Mode Select bit (Bit 14) in the Repeater

Configuration Register is used to choose between CONFIG[1:0]

and CFG bus modes. See Table 75 on page 109.)

1. I = Input, O = Output, I/O = Input/Output, D = Digital, A = Analog, AI = Analog Input,

A I/O = Analog Input/Output, OD = Open Drain, OS = Open Source, PD = Pull Down, PU = Pull Up.

NC = No Clamp. Pad does not clamp input in the absence of power.

2. Pins are 5V tolerant, unless indicated.

9880 Datasheet(PDF) 30 Page - Intel Corporation

9880 Datasheet(HTML) 30 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL