DRV8353FSRTAR datasheet(38/97 Pages) TI

38 / 97 page

DRV835xF

VDRAIN

Power

MOSFETs

48-V

Power

Supply

48-V to 15-V

DC/DC

Figure 8-18. Dual Supply Example

8.3.1.4 Smart Gate Drive Architecture

The DRV835xF gate drivers use an adjustable, complimentary, push-pull topology for both the high-side and

low-side drivers. This topology allows for both a strong pullup and pulldown of the external MOSFET gates.

Additionally, the gate drivers use a smart gate-drive architecture to provide additional control of the external

power MOSFETs, take additional steps to protect the MOSFETs, and allow for optimal tradeoffs between

efficiency and robustness. This architecture is implemented through two components called IDRIVE and TDRIVE

which are detailed in the Section 8.3.1.4.1 section and Section 8.3.1.4.2 section. Figure 8-19 shows the high-

level functional block diagram of the gate driver.

The IDRIVE gate-drive current and TDRIVE gate-drive time should be initially selected based on the parameters

of the external power MOSFET used in the system and the desired rise and fall times (see the Section 9

section).

The high-side gate driver also implements a Zener clamp diode to help protect the external MOSFET gate from

overvoltage conditions in the case of external short-circuit events on the MOSFET.

DRV8350F, DRV8353F, DRV8350RF, DRV8353RF

SLVSFV1 – SEPTEMBER 2020

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DRV8353FSRTAR Datasheet(PDF) 38 Page - Texas Instruments