DRV8353FSRTAR datasheet(7/97 Pages) TI

7 / 97 page

TYPE(1)

DESCRIPTION

NAME

NO.

DRV8353FH

DRV8353FS

INLA

Low-side gate driver control input. This pin controls the output of the low-side gate driver.

INLB

Low-side gate driver control input. This pin controls the output of the low-side gate driver.

INLC

Low-side gate driver control input. This pin controls the output of the low-side gate driver.

MODE

—

PWM input mode setting. This pin is a 4 level input pin set by an external resistor.

nFAULT

Fault indicator output. This pin is pulled logic low during a fault condition and requires an external pullup resistor.

nSCS

—

Serial chip select. A logic low on this pin enables serial interface communication.

SCLK

—

Serial clock input. Serial data is shifted out and captured on the corresponding rising and falling edge on this pin.

SDI

—

Serial data input. Data is captured on the falling edge of the SCLK pin.

SDO

—

Serial data output. Data is shifted out on the rising edge of the SCLK pin. This pin requires an external pullup resistor.

SHA

High-side source sense input. Connect to the high-side power MOSFET source.

SHB

High-side source sense input. Connect to the high-side power MOSFET source.

SHC

High-side source sense input. Connect to the high-side power MOSFET source.

SNA

Shunt amplifier input. Connect to the low-side of the current shunt resistor.

SNB

Shunt amplifier input. Connect to the low-side of the current shunt resistor.

SNC

Shunt amplifier input. Connect to the low-side of the current shunt resistor.

SOA

Shunt amplifier output.

SOB

Shunt amplifier output.

SOC

Shunt amplifier output.

SPA

Low-side source sense and shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the current

shunt resistor.

SPB

Low-side source sense and shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the current

shunt resistor.

SPC

Low-side source sense and shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the current

shunt resistor.

VCP

PWR

Charge pump output. Connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between the VCP and VDRAIN pins.

VDRAIN

High-side MOSFET drain sense input and charge pump reference. Connect to the common point of the MOSFET drains.

VDS

—

VDS monitor trip point setting. This pin is a 7 level input pin set by an external resistor.

VGLS

PWR

11-V internal regulator output. Connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between the VGLS and GND pins.

PWR

Gate driver power supply input. Connect to either VDRAIN or separate gate driver supply voltage. Connect a X5R or X7R,

0.1-µF, VM-rated ceramic and greater then or equal to 10-uF local capacitance between the VM and GND pins.

VREF

PWR

Shunt amplifier power supply input and reference. Connect a X5R or X7R, 0.1-µF, 6.3-V ceramic capacitor between the VREF

and AGND pins.

(1)

PWR = power, I = input, O = output, NC = no connection, OD = open-drain

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SLVSFV1 – SEPTEMBER 2020

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