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DRV8353FSRTAR Datasheet(PDF) 6 Page - Texas Instruments

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Part # DRV8353FSRTAR
Description  DRV835xF 100-V Three-Phase Smart Gate Driver
PDF  97 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

DRV8353FSRTAR Datasheet(HTML) 6 Page - Texas Instruments

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PIN
TYPE(1)
DESCRIPTION
NAME
NO.
DRV8350RFH
DRV8350RFS
VDS
31
—
I
VDS monitor trip point setting. This pin is a 7 level input pin set by an external resistor.
VGLS
2
2
PWR
11-V internal regulator output. Connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between the VGLS and GND pins.
VIN
43
43
PWR
Buck regulator power supply input. Place an X5R or X7R, VM-rated ceramic capacitor between the VIN and GND pins.
VM
5
5
PWR
Gate driver power supply input. Connect to either VDRAIN or separate gate driver supply voltage. Connect a X5R or X7R,
0.1-µF, VM-rated ceramic and greater then or equal to 10-uF local capacitance between the VM and GND pins.
(1)
PWR = power, I = input, O = output, NC = no connection, OD = open-drain
1
CPL
30
GAIN
2
CPH
29
VDS
3
VM
28
IDRIVE
4
VDRAIN
27
MODE
5
VCP
26
nFAULT
6
GHA
25
AGND
7
SHA
24
VREF
8
GLA
23
SOA
9
SPA
22
SOB
10
SNA
21
SOC
Not to scale
Thermal
Pad
Figure 6-5. DRV8353FH RTA Package 40-Pin WQFN
With Exposed Thermal Pad Top View
1
CPL
30
nSCS
2
CPH
29
SCLK
3
VM
28
SDI
4
VDRAIN
27
SDO
5
VCP
26
nFAULT
6
GHA
25
AGND
7
SHA
24
VREF
8
GLA
23
SOA
9
SPA
22
SOB
10
SNA
21
SOC
Not to scale
Thermal
Pad
Figure 6-6. DRV8353FS RTA Package 40-Pin WQFN
With Exposed Thermal Pad Top View
Pin Functions—40-Pin DRV8353F Devices
PIN
TYPE(1)
DESCRIPTION
NAME
NO.
DRV8353FH
DRV8353FS
AGND
25
25
PWR
Device analog ground. Connect to system ground.
CPH
2
2
PWR
Charge pump switching node. Connect a X5R or X7R, 47-nF, VDRAIN-rated ceramic capacitor between the CPH and CPL
pins.
CPL
1
1
PWR
Charge pump switching node. Connect a X5R or X7R, 47-nF, VDRAIN-rated ceramic capacitor between the CPH and CPL
pins.
DVDD
38
38
PWR
5-V internal regulator output. Connect a X5R or X7R, 1-µF, 6.3-V ceramic capacitor between the DVDD and GND pins. This
regulator can source up to 10 mA externally.
ENABLE
31
31
I
Gate driver enable. When this pin is logic low the device goes to a low power sleep mode. An 8 to 40-µs low pulse can be
used to reset fault conditions.
GAIN
30
—
I
Amplifier gain setting. The pin is a 4 level input pin set by an external resistor.
GND
39
39
PWR
Device power ground. Connect to system ground.
GHA
6
6
O
High-side gate driver output. Connect to the gate of the high-side power MOSFET.
GHB
15
15
O
High-side gate driver output. Connect to the gate of the high-side power MOSFET.
GHC
16
16
O
High-side gate driver output. Connect to the gate of the high-side power MOSFET.
GLA
8
8
O
Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
GLB
13
13
O
Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
GLC
18
18
O
Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
IDRIVE
28
—
I
Gate drive output current setting. This pin is a 7 level input pin set by an external resistor.
INHA
32
32
I
High-side gate driver control input. This pin controls the output of the high-side gate driver.
INHB
34
34
I
High-side gate driver control input. This pin controls the output of the high-side gate driver.
INHC
36
36
I
High-side gate driver control input. This pin controls the output of the high-side gate driver.
DRV8350F, DRV8353F, DRV8350RF, DRV8353RF
SLVSFV1 – SEPTEMBER 2020
www.ti.com
6
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Copyright © 2020 Texas Instruments Incorporated
Product Folder Links: DRV8350F DRV8353F DRV8350RF DRV8353RF



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