DRV8353FSRTAR datasheet(58/97 Pages) TI

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Table 8-6. Fault Action and Response (continued)

FAULT

CONDITION

CONFIGURATION

REPORT

GATE DRIVER

RECOVERY

OCP_MODE = 01b

nFAULT

Hi-Z

Retry:

tRETRY

OCP_MODE = 10b

nFAULT

Active

No action

OCP_MODE = 11b or

DIS_SEN = 1b

None

Active

No action

Gate Driver Fault

(GDF)

VGS Stuck > tDRIVE

DIS_GDF = 0b

nFAULT

Hi-Z

Latched:

CLR_FLT, ENABLE Pulse

DIS_GDF = 1b

None

Active

No action

Thermal Warning

(OTW)

TJ > TOTW

OTW_REP = 1b

nFAULT

Active

Automatic:

TJ < TOTW – THYS

OTW_REP = 0b

None

Active

No action

Thermal Shutdown

(OTSD)

TJ > TOTSD

—

nFAULT

Hi-Z

Automatic:

TJ < TOTSD – THYS

8.4 Device Functional Modes

8.4.1 Gate Driver Functional Modes

8.4.1.1 Sleep Mode

The ENABLE pin manages the state of the DRV835xF family of devices. When the ENABLE pin is low, the

device goes to a low-power sleep mode. In sleep mode, all gate drivers are disabled, all external MOSFETs are

disabled, the VCP charge pump and VGLS regulator are disabled, the DVDD regulator is disabled, the sense

amplifiers are disabled, and the SPI bus is disabled. In sleep mode all the device registers will reset to their

default values. The tSLEEP time must elapse after a falling edge on the ENABLE pin before the device goes to

sleep mode. The device comes out of sleep mode automatically if the ENABLE pin is pulled high. The tWAKE time

must elapse before the device is ready for inputs.

In sleep mode and when VVM < VUVLO, all external MOSFETs are disabled. The high-side gate pins, GHx, are

pulled to the SHx pin by an internal resistor and the low-side gate pins, GLx, are pulled to the PGND pin by an

internal resistor.

8.4.1.2 Operating Mode

When the ENABLE pin is high and VVM > VUVLO, the device goes to operating mode. The tWAKE time must

elapse before the device is ready for inputs. In this mode the charge pump, low-side gate regulator, DVDD

regulator, and SPI bus are active

8.4.1.3 Fault Reset (CLR_FLT or ENABLE Reset Pulse)

In the case of device latched faults, the DRV835xF family of devices goes to a partial shutdown state to help

protect the external power MOSFETs and system.

When the fault condition has been removed the device can reenter the operating state by either setting the

CLR_FLT SPI bit on SPI devices or issuing a result pulse to the ENABLE pin on either interface variant. The

ENABLE reset pulse (tRST) consists of a high-to-low-to-high transition on the ENABLE pin. The low period of the

sequence should fall with the tRST time window or else the device will start the complete shutdown sequence.

The reset pulse has no effect on any of the regulators, device settings, or other functional blocks

8.4.2 Buck Regulator Functional Modes

8.4.2.1 Shutdown Mode

The RT/SD pin provides ON and OFF control for the LM5008A. When VSD is below approximately 0.7 V, the

device is in shutdown mode. Both the internal LDO and the switching regulator are off. The quiescent current in

shutdown mode drops to 110 µA (typical) at VIN = 48 V. The LM5008A also employs VCC bias rail undervoltage

protection. If the VCC bias supply voltage is below its UV threshold, the regulator stays off.

8.4.2.2 Active Mode

LM5008A is in active mode when the internal bias rail, VCC, is above its UV threshold. Depending on the load

current, the device operates in either DCM or CCM mode.

DRV8350F, DRV8353F, DRV8350RF, DRV8353RF

SLVSFV1 – SEPTEMBER 2020

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