DS3172 datasheet(177/232 Pages) DALLAS

177 / 232 page

DS3171/DS3172/DS3173/DS3174

177 of 232

Bit 2: Automatic RDI Defeat (ARDID) – When 0, the RDI is automatically generated based received DS3 alarms.

When 1, the RDI is inserted from the register bit TRDI.

Bit 1: Transmit Frame Generation Control (TFGC) – When this bit is zero, the Transmit Frame Processor frame

generation is enabled. The DS3 overhead positions in the incoming DS3 payload will be overwritten with the

internally generated DS3 overhead. When this bit is one, the Transmit Frame Processor frame generation is

disabled. The DS3 overhead positions in the incoming DS3 payload will be passed through to error insertion. Note:

Frame generation will still overwrite the P-bits if PBGE = 1. Also, the DS3 overhead periods can still be overwritten

by overhead insertion.

Bit 0: Transmit Alarm Indication Signal (TAIS) –

0 = Transmit Alarm Indication Signal is not inserted

1 = Transmit Alarm Indication Signal is inserted into data stream payload

T3.TEIR

T3 Transmit Error Insertion Register

(1,3,5,7)1Ah

Bit #

Name

CCPEIE

CPEI

CFBEIE

FBEI

Default

Bit #

Name

Reserved

CPEIE

PEI

FEIC1

FEIC0

FEI

TSEI

MEIMS

Default

Bit 11: Continuous C-bit Parity Error Insertion Enable (CCPEIE) – When 0, single C-bit parity error insertion is

enabled. When 1, continuous C-bit parity error insertion is enabled, and C-bit parity errors will be transmitted

continuously if CPEI is high.

Bit 10: C-bit Parity Error Insertion Enable (CPEI) – When 0, C-bit parity error insertion is disabled. When 1, C-bit

parity error insertion is enabled.

Bit 9: Continuous Far-End Block Error Insertion Enable (CFBEIE) – When 0, single far-end block error

insertion is enabled. When 1, continuous far-end block error insertion is enabled, and far-end block errors will be

transmitted continuously if FBEI is high.

Bit 8: Far-End Block Error Insertion Enable (FBEI) – When 0, far-end block error insertion is disabled. When 1,

far-end block error insertion is enabled.

Bit 6: Continuous P-bit Parity Error Insertion Enable (CPEIE) – When 0, single P-bit parity error insertion is

enabled. When 1, continuous P-bit parity error insertion is enabled, and P-bit parity errors will be transmitted

continuously if PEI is high.

Bit 5: P-bit Parity Error Insertion Enable (PEI) – When 0, P-bit parity error insertion is disabled. When 1, P-bit

parity error insertion is enabled.

Bits 4 to 3: Framing Error Insertion Control (FEIC[1:0]) – These two bits control the framing error event to be

inserted.

00 = F-bit error.

01 = M-bit error.

10 = SEF error.

11 = OOMF error.

Bit 2: Framing Error Insertion Enable (FEI) – When 0, framing error insertion is disabled. When 1, framing error

insertion is enabled.

DS3172 Datasheet(PDF) 177 Page - Dallas Semiconductor

DS3172 Datasheet(HTML) 177 Page - Dallas Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL