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Bit 1: Transmit Single Error Insert (TSEI) – This bit causes an error of the enabled type(s) to be inserted in the

transmit data stream if manual error insertion is disabled (MEIMS = 0). A 0 to 1 transition causes a single error to

be inserted. For a second error to be inserted, this bit must be set to 0, and back to 1. Note: If MEIMS is low, and

this bit transitions more than once between error insertion opportunities, only one error will be inserted.

Bit 0: Manual Error Insert Mode Select (MEIMS) – When 0, error insertion is initiated by the TSEI register bit.

When 1, error insertion is initiated by the transmit manual error insertion signal (TMEI). Note: If TMEI or TSEI is

one, changing the state of this bit may cause an error to be inserted.

12.9.2 Receive DS3 Register Map

The receive DS3 utilizes eleven registers. Two registers are shared for C-Bit and M23 DS3 modes. The M23 DS3

mode does not use the RFEBER or RCPECR count registers.

Table 12-24. Receive DS3 Framer Register Map

Address

(1,3,5,7)20h T3.RCR

T3 Receive Control Register

(1,3,5,7)22h

Reserved

(1,3,5,7)24h T3.RSR1

T3 Receive Status Register #1

(1,3,5,7)26h T3.RSR2

T3 Receive Status Register #2

(1,3,5,7)28h T3.RSRL1

T3 Receive Status Register Latched #1

(1,3,5,7)2Ah T3.RSRL2

T3 Receive Status Register Latched #2

(1,3,5,7)2Ch T3.RSRIE1

T3 Receive Status Register Interrupt Enable #1

(1,3,5,7)2Eh T3.RSRIE2

T3 Receive Status Register Interrupt Enable #2

(1,3,5,7)30h

Reserved

(1,3,5,7)32h

Reserved

(1,3,5,7)34h T3.RFECR

T3 Receive Framing Error Count Register

(1,3,5,7)36h T3.RPECR

T3 Receive P-bit Parity Error Count Register

(1,3,5,7)38h T3.RFBECR

T3 Receive Far-End Block Error Count Register

(1,3,5,7)3Ah T3.RCPECR

T3 Receive C-bit Parity Error Count Register

(1,3,5,7)3Ch

Unused

(1,3,5,7)3Eh

Unused

12.9.2.1 Register Bit Descriptions

T3.RCR

T3 Receive Control Register

(1,3,5,7)20h

Bit #

Name

Reserved

COVHD

MAOD

MDAISI

AAISD

ECC

FECC1

FECC0

Default

Bit #

Name

RAILE

RAILD

RAIOD

RAIAD

ROMD

LIP1

LIP0

FRSYNC

Default

Bit 14: C-bit Overhead Masking Disable (COVHD) – When 0, the C-bit positions will be marked as overhead

(RDENn=0). When 1, the C-bit positions will be marked as data (RDENn=1). This bit is ignored in C-bit DS3 mode

or when the ROMD bit is set to one.

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