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VR4102 Datasheet(PDF) 189 Page - NEC |
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VR4102 Datasheet(HTML) 189 Page - NEC |
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189 / 701 page ![]() CHAPTER 6 EXCEPTION PROCESSING 189 6.4.16 Integer Overflow Exception Cause An Integer Overflow exception occurs when an ADD, ADDI, SUB, DADD, DADDI or DSUB instruction results in a 2’s complement overflow. This exception is not maskable. Processing The common exception vector is used for this exception, and the Ov code in the ExcCode field of the Cause register is set. The EPC register contains the address of the instruction that caused the exception unless the instruction is in a branch delay slot, in which case the EPC register contains the address of the preceding branch instruction and the BD bit of the Cause register is set to 1. Servicing At the time of the exception, the kernel reports the UNIX SIGFPE/FPE_INTOVF_TRAP (floating-point exception/integer overflow) signal to the current process, and this exception is usually fatal. 6.4.17 Watch Exception Cause A Watch exception occurs when a load or store instruction references the physical address specified by the WatchLo/WatchHi registers. The WatchLo/WatchHi registers specify whether a load or store or both could have initiated this exception. When the R bit of the WatchLo register is set to 1: Load instruction When the W bit of the WatchLo register is set to 1: Store instruction When both the R bit and W bit of the WatchLo register are set to 1: Load instruction or store instruction The CACHE instruction never causes a Watch exception. The Watch exception is postponed while the EXL bit in the Status register is set to 1, and Watch exception is only maskable by setting the EXL bit in the Status register to 1. Processing The common exception vector is used for this exception, and the WATCH code in the ExcCode field of the Cause register is set. The EPC register contains the address of the load or store instruction that caused the exception unless it is in a branch delay slot, in which case the EPC register contains the address of the preceding branch instruction and the BD bit of the Cause register is set to 1. |
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