VR4102 datasheet(186/701 Pages) NEC

186 / 701 page

CHAPTER 6 EXCEPTION PROCESSING

186

6.4.11 System Call Exception

Cause

A System Call exception occurs during an attempt to execute the SYSCALL instruction. This exception is not

maskable.

Processing

The common exception vector is used for this exception, and the Sys code in the ExcCode field of the Cause

The EPC register contains the address of the SYSCALL instruction unless it is in a branch delay slot, in which

case the EPC register contains the address of the preceding branch instruction.

If the SYSCALL instruction is in a branch delay slot, the BD bit of the Status register is set to 1; otherwise this bit

is cleared.

Servicing

When this exception occurs, control is transferred to the applicable system routine.

To resume execution, the EPC register must be altered so that the SYSCALL instruction does not re-execute; this

is accomplished by adding a value of 4 to the EPC register before returning.

If a SYSCALL instruction is in a branch delay slot, interpretation of the branch instruction is required to resume

execution.

6.4.12 Breakpoint Exception

Cause

A Breakpoint exception occurs when an attempt is made to execute the BREAK instruction. This exception is not

maskable.

Processing

The common exception vector is used for this exception, and the BP code in the ExcCode field of the Cause

The EPC register contains the address of the BREAK instruction unless it is in a branch delay slot, in which case

the EPC register contains the address of the preceding branch instruction.

If the BREAK instruction is in a branch delay slot, the BD bit of the Status register is set to 1; otherwise this bit is

cleared.

Servicing

When the Breakpoint exception occurs, control is transferred to the applicable system routine.

Additional

distinctions can be made by analyzing the unused bits of the BREAK instruction (bits 25 to 6), and loading the

contents of the instruction whose address the EPC register contains. A value of 4 must be added to the contents

of the EPC register to locate the instruction if it resides in a branch delay slot.

To resume execution, the EPC register must be altered so that the BREAK instruction does not re-execute; this is

accomplished by adding a value of 4 to the EPC register before returning.

If a BREAK instruction is in a branch delay slot, interpretation (decoding) of the branch instruction is required to

resume execution.

VR4102 Datasheet(PDF) 186 Page - NEC