VR4102 datasheet(183/701 Pages) NEC

183 / 701 page

CHAPTER 6 EXCEPTION PROCESSING

183

(3) TLB Modified Exception

Cause

The TLB Modified exception occurs when the TLB entry that matches with the virtual address referenced by the

store instruction is valid (bit V is 1) but is not writable (bit D is 0). This exception is not maskable.

Processing

The common exception vector is used for this exception, and the Mod code in the ExcCode field of the Cause

When this exception occurs, the BadVAddr, Context, Xcontext, and EntryHi registers contain the virtual address

that failed address translation.

The EntryHi register also contains the ASID from which the translation fault

occurred. The contents of the EntryLo register are undefined.

The EPC register contains the address of the instruction that caused the exception unless that instruction is in a

branch delay slot, in which case the EPC register contains the address of the preceding branch instruction and

the BD bit of the Cause register is set to 1.

Servicing

The kernel uses the failed virtual address or virtual page number to identify the corresponding access control bits.

The page identified may or may not permit write accesses; if writes are not permitted, a write protection violation

occurs.

If write accesses are permitted, the page frame is marked dirty (/writable) by the kernel in its own data structures.

The TLBP instruction places the index of the TLB entry that must be altered into the Index register. The word

data containing the physical page frame and access control bits (with the D bit set to 1) is loaded to the EntryLo

VR4102 Datasheet(PDF) 183 Page - NEC