VR4102 datasheet(179/701 Pages) NEC

179 / 701 page

CHAPTER 6 EXCEPTION PROCESSING

179

6.4.6 NMI Exception

Cause

The Nonmaskable Interrupt (NMI) exception occurs in response to the input of the NMI signal (internal). This

interrupt is not maskable; it occurs regardless of the settings of the EXL, ERL, and the IE bits in the Status

Processing

The CPU provides a special interrupt vector for this exception:

4 0xBFC0 0000 (virtual) in 32-bit mode

4 0xFFFF FFFF BFC0 0000 (virtual) in 64-bit mode

This vector is located within unmapped and uncached address space so that the cache and TLB need not be

initialized to process an NMI interrupt. The SR bit of the Status register is set to 1 to distinguish this exception

from a Cold Reset exception.

Unlike Cold Reset and Soft Reset, but like other exceptions, NMI is taken only at instruction boundaries. The

states of the caches and memory system are preserved by this exception.

When this exception occurs, the contents of all registers are preserved except for the following registers:

4 When ERL bit of the Status register is 0, the program counter’s value at the exception occurrence is saved

to the EPC register.

4 The TS bit of the Status register is cleared to 0.

4 The ERL, SR, and BEV bits of the Status register are set to 1.

Servicing

The NMI exception is serviced by:

4 Preserving the current processor states for diagnostic tests

4 Reinitializing the system in the same way as for a Cold Reset exception

VR4102 Datasheet(PDF) 179 Page - NEC