VR4102 datasheet(181/701 Pages) NEC

181 / 701 page

CHAPTER 6 EXCEPTION PROCESSING

181

6.4.8 TLB Exceptions

Three types of TLB exceptions can occur:

TLB Refill exception occurs when there is no TLB entry that matches a referenced address.

A TLB Invalid exception occurs when a TLB entry that matches a referenced virtual address is marked as

being invalid (with the V bit set to 0).

The TLB Modified exception occurs when a TLB entry that matches a virtual address referenced by the

store instruction is marked as being valid (with the V bit set to 1).

The following three sections describe these TLB exceptions.

(1) TLB Refill Exception (32-bit Space Mode)/XTLB Refill Exception (64-bit Space Mode)

Cause

The TLB Refill exception occurs when there is no TLB entry to match a reference to a mapped address space.

This exception is not maskable.

Processing

There are two special exception vectors for this exception; one for references to 32-bit address spaces, and one

for references to 64-bit address spaces. The UX, SX, and KX bits of the Status register determine whether the

user, supervisor or kernel address spaces referenced are 32-bit or 64-bit spaces. When the EXL bit of the Status

exception vector is referenced.

This exception sets the TLBL or TLBS code in the ExcCode field of the Cause register. If this exception has been

caused by an instruction reference or load operation, TLBL is set. If it has been caused by a store operation,

TLBS is set.

When this exception occurs, the BadVAddr, Context, XContext and EntryHi registers hold the virtual address that

failed address translation. The EntryHi register also contains the ASID from which the translation fault occurred.

The Random register normally contains a valid location in which to place the replacement TLB entry.

The

contents of the EntryLo register are undefined.

The EPC register contains the address of the instruction that caused the exception, unless this instruction is in a

branch delay slot, in which case the EPC register contains the address of the preceding branch instruction and

the BD bit of the Cause register is set to 1.

Servicing

To service this exception, the contents of the Context or XContext register are used as a virtual address to fetch

memory words containing the physical page frame and access control bits for a pair of TLB entries. The memory

word is written into the TLB entry by using the EntryLo0, EntryLo1, or EntryHi register.

It is possible that the physical page frame and access control bits are placed in a page where the virtual address

is not resident in the TLB.

This condition is processed by allowing a TLB Refill exception in the TLB Refill

exception handler. In this case, the common exception vector is used because the EXL bit of the Status register

is set to 1.

VR4102 Datasheet(PDF) 181 Page - NEC