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VR4102 Datasheet(PDF) 176 Page - NEC |
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VR4102 Datasheet(HTML) 176 Page - NEC |
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176 / 701 page  CHAPTER 6 EXCEPTION PROCESSING 176 6.4.3 Priority of Exceptions While more than one exception can occur for a single instruction, only the exception with the highest priority is reported. Table 6-5 lists the priorities. Table 6-5. Exception Priority Order Priority Exceptions High n ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ p Low Cold Reset Soft Reset NMI Address Error (instruction fetch) TLB/XTLB Refill (instruction fetch) TLB Invalid (instruction fetch) Cache Error (instruction fetch) Bus Error (instruction fetch) System Call Breakpoint Coprocessor Unusable Reserved Instruction Trap Integer Overflow Address Error (data access) TLB/XTLB Refill (data access) TLB Invalid (data access) TLB Modified (data write) Cache Error (data access) Watch Bus Error (data access) Interrupt (other than NMI) Hereafter, handling exceptions by hardware is referred to as “process”, and handling exception by software is referred to as “service”. |
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