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VR4102 Datasheet(PDF) 292 Page - NEC |
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VR4102 Datasheet(HTML) 292 Page - NEC |
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292 / 701 page  CHAPTER 14 ICU (INTERRUPT CONTROL UNIT) 292 How an interrupt request is notified to the CPU core is shown below. If an interrupt request occurs in the peripheral units, the corresponding bit in the interrupt indication register of Level 2 (xxxINTREG) is set to 1. The interrupt indication register is ANDed bit-wise with the corresponding interrupt mask register of Level 2 (MxxxINTREG). If the occurred interrupt request is enabled (set to 1) in the mask register, the interrupt request is notified to the interrupt indication register of Level 1 (SYSINTREG) and the corresponding bit is set to 1. At this time, the interrupt requests from the same register of Level 2 are notified to the SYSINTREG as a single interrupt request. Interrupt requests from some units directly set their corresponding bits in the SYSINTREG. The SYSINTREG is ANDed bit-wise with the interrupt mask register of Level 1 (MSYSINTREG). If the interrupt request is enabled by MSYSINTREG (set to 1), a corresponding interrupt request signal is output from the ICU to the CPU core. battint is connected to the NMI or Int0 signal of the CPU core (selected by setting of NMIREG). rtc_long signals are connected to the Int3 signal of the CPU core. The other interrupt requests are connected to the Int0 signal of the CPU core as a one interrupt request. The following figure shows an outline of interrupt control in the ICU. |
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