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VR4102 Datasheet(PDF) 313 Page - NEC

Part # VR4102
Description  64/32-bit Microprocessor
PDF  701 Pages
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Manufacturer  NEC [NEC]
Direct Link  http://www.nec.com/
Logo NEC - NEC

VR4102 Datasheet(HTML) 313 Page - NEC

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CHAPTER 14 ICU (INTERRUPT CONTROL UNIT)
313
14.2.17 FIRINTREG (0x0B00 0204)
Bit
D15
D14
D13
D12
D11
D10
D9
D8
Name
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
R/W
R
RR
RRR
R
R
RTCRST
0
0
0
0
0
0
0
0
Other resets
0
0
0
0
0
0
0
0
Bit
D7
D6D5
D4D3D2
D1
D0
Name
Reserved
Reserved
Reserved
FIRINT
FDPINT[4]
FDPINT[3]
FDPINT[2]
FDPINT[1]
R/W
R
RR
RRR
R
R
RTCRST
0
0
0
0
0
0
0
0
Other resets
0
0
0
0
0
0
0
0
Bit
Name
Function
D[15..5]
Reserved
Write 0 when writing. 0 is returned after a read.
D[4]
FIRINT
Interrupt from FIR unit
1 : Occurred
0 : Normal
D[3]
FDPINT[4]
FIR DMA buffer (receive side) 2 page interrupt
1 : Occurred
0 : Normal
D[2]
FDPINT[3]
FIR DMA buffer (transmit side) 2 page interrupt
1 : Occurred
0 : Normal
D[1]
FDPINT[2]
FIR DMA buffer (receive side) 1 page interrupt
1 : Occurred
0 : Normal
D[0]
FDPINT[1]
FIR DMA buffer (transmit side) 1 page interrupt
1 : Occurred
0 : Normal
This register indicates when various FIR-related interrupts occur.
When FDPINT[4] or FDPINT[3] is set to 1, the VR4102 stops the DMA requests. When FDPINT[2] or FDPINT[1]
is set to 1 during the FDPCNT bit of the DPCNTR register (0x0C00 004C) is set to 1 (DMA buffer 1 page interrupt is
enabled), the VR4102 stops the DMA requests.



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