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VR4102 Datasheet(PDF) 316 Page - NEC |
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VR4102 Datasheet(HTML) 316 Page - NEC |
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316 / 701 page  CHAPTER 14 ICU (INTERRUPT CONTROL UNIT) 316 14.2.20 MFIRINTREG (0x0B00 020A) Bit D15 D14 D13 D12 D11 D10 D9 D8 Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved R/W R RR RRR R R RTCRST 0 0 0 0 0 0 0 0 Other resets 0 0 0 0 0 0 0 0 Bit D7 D6D5 D4D3D2 D1 D0 Name Reserved Reserved Reserved FIRINT FDPINT[4] FDPINT[3] FDPINT[2] FDPINT[1] R/W R R R R/W R/W R/W R/W R/W RTCRST 0 0 0 0 0 0 0 0 Other resets 0 0 0 0 0 0 0 0 Bit Name Function D[15..5] Reserved Write 0 when writing. 0 is returned after a read. D4 FIRINT FIR unit interrupt enable 1 : Enable 0 : Prohibit D[3] FDPINT[4] FIR DMA buffer 2 page interrupt (receive side) enable 1 : Enable 0 : Prohibit D[2] FDPINT[3] FIR DMA buffer 2 page interrupt (transmit side) enable 1 : Enable 0 : Prohibit D[1] FDPINT[2] FIR DMA buffer 1 page interrupt (receive side) enable 1 : Enable 0 : Prohibit D[0] FDPINT[1] FIR DMA buffer 1 page interrupt (transmit side) enable 1 : Enable 0 : Prohibit This register is used to mask various FIR-related interrupts. |
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