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VR4102 Datasheet(PDF) 444 Page - NEC

Part # VR4102
Description  64/32-bit Microprocessor
PDF  701 Pages
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Manufacturer  NEC [NEC]
Direct Link  http://www.nec.com/
Logo NEC - NEC

VR4102 Datasheet(HTML) 444 Page - NEC

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CHAPTER 22 DSIU (DEBUG SERIAL INTERFACE UNIT)
444
22.2.9 ASIS0REG (0x0B00 01B0)
Bit
D15
D14
D13
D12
D11
D10
D9
D8
Name
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
R/W
R
RR
RRR
R
R
RTCRST
0
0
0
0
0
0
0
0
Other resets
0
0
0
0
0
0
0
0
Bit
D7
D6D5
D4D3D2
D1
D0
Name
SOT0
Reserved
Reserved
Reserved
Reserved
PE0
FE0
OVE0
R/W
R
RR
RRR
R
R
RTCRST
0
0
0
0
0
0
0
0
Other resets
0
0
0
0
0
0
0
0
Bit
Name
Function
D[15:8]
Reserved
Write 0 when writing. 0 is returned after a read.
D[7]
SOT0
Transmit mode status
1 : Transmission start
0 : Transmission complete
D[6:3]
Reserved
Write 0 when writing. 0 is returned after a read.
D[2]
PE0
Parity error status
1 : Parity error
0 : Normal
D[1]
FE0
Framing error status
1 : Framing error
0 : Normal
D[0]
OVE0
Overrun error status
1 : Overrun error status
0 : Normal
This register indicates the debug serial transmit/receive status.
A write to the TXS0RREG or TXS0LREG register sets “1” to the SOT0 bit. When the transmission is completed,
“1” is set to the INTR0REG register’s INTST0 bit and the SOT0 bit is cleared to zero. This bit can be used as a
means of determining whether or not it is possible to write to the transmission shift register when transmitting data in
debug serial mode.
If the received data contains a parity error, “1” is set to the PE0 bit. If the stop bit is not detected, “1” is set to the
FE0 bit.
An overrun error occurs and “1” is set to the OVE0 bit if the sequencer completes the next receive processing
before receive data is read from the receive buffer. When an overrun error occurs, the old data in the receive buffer
is overwritten by the newly received data.



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