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VR4102 Datasheet(PDF) 445 Page - NEC

Part # VR4102
Description  64/32-bit Microprocessor
PDF  701 Pages
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Manufacturer  NEC [NEC]
Direct Link  http://www.nec.com/
Logo NEC - NEC

VR4102 Datasheet(HTML) 445 Page - NEC

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CHAPTER 22 DSIU (DEBUG SERIAL INTERFACE UNIT)
445
22.2.10 INTR0REG (0x0B00 01B2)
Bit
D15
D14
D13
D12
D11
D10
D9
D8
Name
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
R/W
R
RR
RRR
R
R
RTCRST
0
0
0
0
0
0
0
0
Other resets
0
0
0
0
0
0
0
0
Bit
D7
D6D5
D4D3D2
D1
D0
Name
Reserved
Reserved
Reserved
Reserved
INTDCD
INTSER0
INTSR0
INTST0
R/W
R
R
R
R
R/W
R/W
R/W
R/W
RTCRST
0
0
0
0
0
0
0
0
Other resets
0
0
0
0
0
0
0
0
Bit
Name
Function
D[15:4]
Reserved
Write 0 when writing. 0 is returned after a read.
D[3]
INTDCD
CTS# change interrupt. Cleared to 0 when 1 is written.
1 : CTS change interrupt
0 : Normal
D[2]
INTSER0
Debug serial receive error interrupt. Cleared to 0 when 1 is written.
1 : Error interrupt
0 : Normal
D[1]
INTSR0
Debug serial receive complete interrupt. Cleared to 0 when 1 is written.
1 : Receive complete
0 : Other
D[0]
INTST0
Debug serial transmit complete interrupt. Cleared to 0 when 1 is written.
1 : Transmit complete
0 : Other
This register indicates interrupt events that occur during debug serial transmission.
When debug serial operations are in the reception-enable mode, and either the PE0 bit, FE0 bit, or OVE0 bit in
the ASIS0REG has been set, “1” is set to the INTSER0 bit.
When debug serial operations are in the reception-enable mode, and receive data is transferred to the receive
buffer, “1” is set to the INTSR0 bit. When one frame of transmit data is sent from the transmit register, “1” is set to
the INTST0 bit.
When the CTS# (flow control signal from an external agent) is changed, “1” is set to INTDCD bit.



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