VR4102 datasheet(464/701 Pages) NEC

464 / 701 page

CHAPTER 24 SIU (SERIAL INTERFACE UNIT)

464

24.2.4 SIUIE (0x0C00 0001: LCR[7] = 0)

Bit

D6D5

D4D3D2

Name

Reserved

IE[3]

IE[2]

IE[1]

IE[0]

R/W

RTCRST

Other resets

Bit

Name

Function

D[7..4]

Reserved

Write 0 when writing. 0 is returned after read.

D[3]

IE[3]

Modem status interrupt

1 : Interrupt enable

0 : Interrupt prohibit

D[2]

IE[2]

Receive status interrupt

1 : Interrupt enable

0 : Interrupt prohibit

D[1]

IE[1]

Transmitter holding register empty interrupt

1 : Interrupt enable

0 : Interrupt prohibit

D[0]

IE[0]

Receive data interrupt or timeout interrupt in FIFO mode

1 : Interrupt enable

0 : Interrupt prohibit

This register is used to specify interrupt enable/prohibit settings for the five types of interrupt used by the SIU.

These interrupts can be used to make the corresponding interrupt output signal (INTR) active.

Overall use of interrupt functions can be halted by setting bit 0 to bit 3 of the interrupt enable register (IER) to

zero. If one or more of the bits from bit 0 to bit 3 has a value of 1, the corresponding interrupt is enabled.

When interrupts are prohibited, “pending” is not displayed in the IIR[0] bit even when the interrupt condition has

been met and INTR output does not become active.

Other functions in the system are not affected even though interrupts are prohibited and the settings in the line

status register and modem status register are valid.

To access this register, set LCR[7] (bit 7 of SIULC register) to 0.

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