VR4102 datasheet(538/701 Pages) NEC

538 / 701 page

CHAPTER 27 CPU INSTRUCTION SET DETAILS

538

BC0T

Branch On Coprocessor 0 True

BC0T

0 1 0 0 0

COPz

0 1 0 0 X X

Note

BCT

0 0 0 0 1

offset

26 25

21 20

16 15

Format:

BC0T offset

Description:

A branch target address is computed from the sum of the address of the instruction in the delay slot and the 16-bit

offset, shifted left two bits and sign-extended. If the coprocessor 0’s condition signal (CpCond: Status register bit-

18 CH field) is true, then the program branches to the target address, with a delay of one instruction.

Because the condition line is sampled during the previous instruction, there must be at least one instruction

between this instruction and a coprocessor instruction that changes the condition line.

Operation:

T-1:

condition <- SR18

target <- (offset15)

14 || offset || 02

T+1: if condition then

PC <- PC + target

endif

T-1:

condition <- SR18

target <- (offset15)

46 || offset || 02

T+1: if condition then

PC <- PC + target

endif

Exceptions:

Coprocessor unusable exception

Note

See the opcode table below, or 27.6 CPU INSTRUCTION OPCODE BIT ENCODING.

Opcode Table:

BC0T

Opcode

Coprocessor

number

BC sub-opcode

Branch condition

VR4102 Datasheet(PDF) 538 Page - NEC

VR4102 Datasheet(HTML) 538 Page - NEC

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL