VR4102 datasheet(536/701 Pages) NEC

536 / 701 page

CHAPTER 27 CPU INSTRUCTION SET DETAILS

536

BC0F

Branch On Coprocessor 0 False

BC0F

0 1 0 0 0

COPz

0 1 0 0 X X

Note

BCF

0 0 0 0 0

offset

26 25

21 20

16 15

Format:

BC0F offset

Description:

A branch target address is computed from the sum of the address of the instruction in the delay slot and the 16-bit

offset, shifted left two bits and sign-extended. If coprocessor 0’s condition signal (CpCond: Status register bit-18

CH field), as sampled during the previous instruction, is false, then the program branches to the target address

with a delay of one instruction.

Because the condition line is sampled during the previous instruction, there must be at least one instruction

between this instruction and a coprocessor instruction that changes the condition line.

Operation:

T-1:

condition <- not SR18

target <- (offset15)

14 || offset || 02

T+1: if condition then

PC <- PC + target

endif

T-1:

condition <- not SR18

target <- (offset15)

46 || offset || 02

T+1: if condition then

PC <- PC + target

endif

Exceptions:

Coprocessor unusable exception

Note

See the opcode table below, or 27.6 CPU INSTRUCTION OPCODE BIT ENCODING.

Opcode Table:

BC0F

Opcode

Coprocessor

number

BC sub-opcode

Branch condition

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