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VR4102 Datasheet(PDF) 532 Page - NEC |
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VR4102 Datasheet(HTML) 532 Page - NEC |
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532 / 701 page ![]() CHAPTER 27 CPU INSTRUCTION SET DETAILS 532 ADDIU Add Immediate Unsigned ADDIU rs ADDIU 0 0 1 0 0 1 rt immediate 31 26 25 21 20 16 15 0 65 5 16 Format: ADDIU rt, rs, immediate Description: The 16-bit immediate is sign-extended and added to the contents of general register rs to form the result. The result is placed into general register rt. No integer overflow exception occurs under any circumstances. In 64-bit mode, the operand must be valid sign-extended, 32-bit values. The only difference between this instruction and the ADDI instruction is that ADDIU never causes an integer overflow exception. Operation: 32 T: GPR [rt] <- GPR [rs] + (immediate15) 16 || immediate15...0 64 T: temp <- GPR [rs] + (immediate15) 48 || immediate15...0 GPR [rt] <- (temp31) 32 || temp31...0 Exceptions: None |
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