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VR4102 Datasheet(PDF) 533 Page - NEC |
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VR4102 Datasheet(HTML) 533 Page - NEC |
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533 / 701 page  CHAPTER 27 CPU INSTRUCTION SET DETAILS 533 ADDU Add Unsigned ADDU rs SPECIAL 0 0 0 0 0 0 rt rd 0 0 0 0 0 0 ADDU 1 0 0 0 0 1 31 26 25 21 20 16 15 11 10 6 5 0 6 5555 6 Format: ADDU rd, rs, rt Description: The contents of general register rs and the contents of general register rt are added to form the result. The result is placed into general register rd. No integer overflow exception occurs under any circumstances. In 64-bit mode, the operands must be valid sign-extended, 32-bit values. The only difference between this instruction and the ADD instruction is that ADDU never causes an integer overflow exception. Operation: 32 T: GPR [rd] <- GPR [rs] + GPR [rt] 64 T: temp <- GPR [rs] + GPR [rt] GPR [rd] <- (temp31) 32 || temp31...0 Exceptions: None |
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