VR4102 datasheet(528/701 Pages) NEC

528 / 701 page

CHAPTER 27 CPU INSTRUCTION SET DETAILS

528

Table 27-3. Access Type Specifications for Loads/Stores

Access Type Mnemonic

Value

Meaning

DOUBLEWORD

SEPTIBYTE

SEXTIBYTE

QUINTIBYTE

WORD

TRIPLEBYTE

HALFWORD

BYTE

8 bytes (64 bits)

7 bytes (56 bits)

6 bytes (48 bits)

5 bytes (40 bits)

4 bytes (32 bits)

3 bytes (24 bits)

2 bytes (16 bits)

1 byte (8 bits)

The bytes within the addressed doubleword which are used can be determined directly from the access type and

the three low-order bits of the address.

27.3 JUMP AND BRANCH INSTRUCTIONS

All jump and branch instructions have an architectural delay of exactly one instruction. That is, the instruction

immediately following a jump or branch (that is, occupying the delay slot) is always executed while the target

instruction is being fetched from storage. A delay slot may not itself be occupied by a jump or branch instruction;

however, this error is not detected and the results of such an operation are undefined.

If an exception or interrupt prevents the completion of a legal instruction during a delay slot, the hardware sets the

EPC register to point at the jump or branch instruction that precedes it. When the code is restarted, both the jump or

branch instructions and the instruction in the delay slot are reexecuted.

Because jump and branch instructions may be restarted after exceptions or interrupts, they must be restartable.

Therefore, when a jump or branch instruction stores a return link value, register

r31 (the register in which the link is

stored) may not be used as a source register.

Since instructions must be word-aligned, a Jump Register or Jump and Link Register instruction must use a

address exception will occur when the jump target instruction is subsequently fetched.

27.4 SYSTEM CONTROL COPROCESSOR (CP0) INSTRUCTIONS

There are some special limitations imposed on operations involving CP0 that is incorporated within the CPU.

Although load and store instructions to transfer data to/from coprocessors and to move control to/from coprocessor

instructions are generally permitted by the MIPS architecture, CP0 is given a somewhat protected status since it has

responsibility for exception handling and memory management.

Therefore, the move to/from coprocessor

instructions are the only valid mechanism for writing to and reading from the CP0 registers.

Several CP0 instructions are defined to directly read, write, and probe TLB entries and to modify the operating

modes in preparation for returning to User mode or interrupt-enabled states.

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