VR4102 datasheet(525/701 Pages) NEC

525 / 701 page

525

CHAPTER 27 CPU INSTRUCTION SET DETAILS

This chapter provides a detailed description of the operation of each VR4102 instruction in both 32- and 64-bit

modes. The instructions are listed in alphabetical order.

27.1 INSTRUCTION NOTATION CONVENTIONS

In this chapter, all variable subfields in an instruction format (such as

rs, rt, immediate, etc.) are shown in

lowercase names.

For the sake of clarity, we sometimes use an alias for a variable subfield in the formats of specific instructions.

For example, we use

rs = base in the format for load and store instructions. Such an alias is always lower case,

since it refers to a variable subfield.

Figures with the actual bit encoding for all the mnemonics are located at the end of this chapter, and the bit

encoding also accompanies each instruction.

In the instruction descriptions that follow, the Operation section describes the operation performed by each

instruction using a high-level language notation. The VR4102 can operate as either a 32- or 64-bit microprocessor

and the operation for both modes is included with the instruction description.

Special symbols used in the notation are described in Table 27-1.

VR4102 Datasheet(PDF) 525 Page - NEC