VR4102 datasheet(523/701 Pages) NEC

523 / 701 page

CHAPTER 26 FIR (FAST IrDA INTERFACE UNIT)

523

26.2.20 RXFL (0x0C00 0074)

Bit

D15

D14

D13

D12

D11

D10

Name

Reserved

RXFL12

RXFL11

RXFL10

RXFL9

RXFL8

R/W

RRR

RTCRST

000

Other resets

Bit

D7D6D5

D4D3

D2D1

Name

RXFL7

RXFL6

RXFL5

RXFL4

RXFL3

RXFL2

RXFL1

RXFL0

R/W

RRR

RTCRST

000

Other resets

Bit

Name

Function

D15 to

D13

Reserved

Write 0 when writing. 0 is returned after a read.

D12 to D0

RXFL12 to RXFL0

Receive frame size.

[Function]

This register functions as prebuffer address for data read from the receive frame size data store FIFO, in which

data of up to 7 frames can be stored.

Setting value = transmit size – 1

Setting range = 1 to 2 Kbytes

The FIFO is initialized by setting bit 1 of the FSR register.

(1) Write

When the frame reception is completed after its data is transferred (even if only 1 byte) to the receive FIFO, the

sequencer writes the current transfer data size to this register, and the write pointer is incremented.

When the frame reception is completed before its data is transferred to the receive FIFO, write operation is not

performed (lost frame).

(2) Read

The read pointer is enabled to be incremented by reading valid data from the RXSTS register, and the next data

can be read.

[Caution]

If a receive operation ends abnormally, the data size transferred to the receive FIFO at that time is written to this

When the data of 7 frames are stored, the receive line is automatically masked. Therefore, the frame whose

receive result cannot be stored is not transferred to the FIFO.

The update condition of the read pointer of the receive frame size store FIFO is also valid in the test mode.

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