VR4102 datasheet(527/701 Pages) NEC

527 / 701 page

CHAPTER 27 CPU INSTRUCTION SET DETAILS

527

(1) Instruction notation examples

The following examples illustrate the application of some of the instruction notation conventions:

Example #1:

GPR [rt] <- immediate || 0

Sixteen zero bits are concatenated with an immediate value (typically 16 bits), and the 32-bit string (with

the lower 16 bits set to zero) is assigned to General-purpose register

rt.

Example #2:

(immediate15)

16 || immediate15...0

Bit 15 (the sign bit) of an immediate value is extended for 16 bit positions, and the result is concatenated

with bits 15 through 0 of the immediate value to form a 32-bit sign extended value.

27.2 LOAD AND STORE INSTRUCTIONS

In the VR4102 implementation, the instruction immediately following a load may use the loaded contents of the

still desirable, although not required for functional code.

In the load and store descriptions, the functions listed in Table 27-2 are used to summarize the handling of virtual

addresses and physical memory.

Table 27-2. Load and Store Common Functions

Function

Meaning

Address Translation

Uses the TLB to find the physical address given the virtual address.

The function fails and an

exception is taken if the required translation is not present in the TLB.

Load Memory

Uses the cache and main memory to find the contents of the word containing the specified physical

address. The low-order three bits of the address and the Access Type field indicate which of each

of the four bytes within the data word need to be returned. If the cache is enabled for this access,

the entire word is returned and loaded into the cache.

Store Memory

Uses the cache, write buffer, and main memory to store the word or part of word specified as data in

the word containing the specified physical address. The low-order three bits of the address and the

Access Type field indicate which of each of the four bytes within the data word should be stored.

As shown in Table 27-3, the Access Type field indicates the size of the data item to be loaded or stored.

Regardless of access type or byte-numbering order (endianness), the address specifies the byte which has the

smallest byte address in the addressed field. This is the rightmost byte in the VR4102 since it supports the little-

endian order only.

VR4102 Datasheet(PDF) 527 Page - NEC