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VR4102 Datasheet(PDF) 519 Page - NEC

Part # VR4102
Description  64/32-bit Microprocessor
PDF  701 Pages
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Manufacturer  NEC [NEC]
Direct Link  http://www.nec.com/
Logo NEC - NEC

VR4102 Datasheet(HTML) 519 Page - NEC

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CHAPTER 26 FIR (FAST IrDA INTERFACE UNIT)
519
26.2.17 RXSTS (0x0C00 006C)
Bit
D15
D14
D13
D12
D11
D10
D9
D8
Name
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
R/W
RRR
RR
RR
R
RTCRST
000
00
00
0
Other resets
0
0
0
0
0
0
0
0
Bit
D7D6D5
D4D3
D2D1
D0
Name
Valid
Reserved
Reserved
RXF_OV
CRC_ERR
ABORT
MRXF_OV
Reserved
R/W
RRR
RR
RR
R
RTCRST
000
00
00
0
Other resets
0
0
0
0
0
0
0
0
Bit
Name
Function
D15 to D8
Reserved
Write 0 when writing. 0 is returned after a read.
D7
Valid
Valid status in the indication status.
This bit is set to 1 when received data of one frame is read completely.
0: Received data read not completed
1: Received data read completed
D6 and D5
Reserved
Write 0 when writing. 0 is returned after a read.
D4
RXF_OV
Receive FIFO overrun error.
This bit is set to 1 when a receive operation is stopped by receive FIFO’s overrun.
0: Normal
1: Overrun
D3
CRC_ERR
CRC Error.
This bit is set t o 1 when the receive result CRC does not match with expected
value.
0: Normal
1: CRC error
D2
ABORT
Abort detection error.
This bit is set to 1 when a receive operation is stopped by abort frame detection.
0: Normal
1: Abort error
D1
MRXF_OV
Maximum receive frame size error.
This bit is set to 1 when a receive operation is stopped by maximum receive frame
size overrun.
0: Normal
1: Overrun
D0
Reserved
Write 0 when writing. 0 is returned after a read.
[Function]
Reads data from the receive status store FIFO, in which data of up to 7 frames can be stored.
The FIFO is initialized by setting bit 1 of the FSR register.
Received status FIFO is used as follows.



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