VR4102 datasheet(515/701 Pages) NEC

515 / 701 page

CHAPTER 26 FIR (FAST IrDA INTERFACE UNIT)

515

26.2.15 RXIR (0x0C00 0068)

Bit

D15

D14

D13

D12

D11

D10

Name

Reserved

R/W

RRR

RTCRST

000

Other resets

Bit

D7D6D5

D4D3

D2D1

Name

RX_BUSY

END_DATA

LAST_RFL

RX_TH_O

Reserved

RXF_FULL

RXF_EMP

R/W

RRR

RTCRST

000

Other resets

Bit

Name

Function

D15 to D8

Reserved

Write 0 when writing. 0 is returned after a read.

RX_BUSY

Reception busy.

This bit is set to 1 during the period between when PA (in FIR) or STA (in MIR) is

detected and when reception ends.

0: Not Busy

1: Busy

END_DATA

Frame last data status.

This bit indicates whether the last data of frame that is received completely exists

or not in the FIFO.

0: Normal

1: Exists

LAST_RFL

Last reception frame status.

This bit is set (to 1) when the reception result (frame size and status) of the 7th

frame is stored.

0: Normal

1: Result is stored

RX_TH_O

Reception FIFO threshold over status.

This bit indicates whether or not the data size within the reception FIFO exceeds

the threshold.

0: Normal

1: Excesses

D3 and D2

Reserved

Write 0 when writing. 0 is returned after a read.

RXF_FULL

Reception FIFO full status.

This bit indicates that there is no writable space in the reception FIFO.

0: Normal

1: No writable space

RXF_EMP

Reception FIFO empty status.

This bit indicates whether or not data to be read exists in the reception FIFO.

0: Normal

1: Exists

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