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VR4102 Datasheet(PDF) 513 Page - NEC |
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VR4102 Datasheet(HTML) 513 Page - NEC |
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513 / 701 page ![]() CHAPTER 26 FIR (FAST IrDA INTERFACE UNIT) 513 26.2.13 DMAER (0x0C00 0064) Bit D15 D14 D13 D12 D11 D10 D9 D8 Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved R/W RRR RR RR R RTCRST 000 00 00 0 Other resets 0 0 0 0 0 0 0 0 Bit D7D6D5 D4D3 D2D1 D0 Name Reserved Reserved Reserved Reserved Reserved Reserved DMA_BUSY DMA_EN R/W RRR RR RR R/W RTCRST 000 00 00 0 Other resets 0 0 0 0 0 0 0 0 Bit Name Function D15 to D2 Reserved Write 0 when writing. 0 is returned after a read. D1 DMA_BUSY DMA busy status 1: Busy 0: Not Busy D0 DMA_EN This bit is used as a DMA operation enable trigger. 1: Enable 0: Disable Note that the DMA is not stopped by clearing this bit (to 0). [Function] The DMA_BUSY bit is set automatically by setting the DMA_EN bit to 1. The DMA_BUSY bit is cleared when bit 0 of the FSR register is set or when all frame transmit data is written. |
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