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VR4102 Datasheet(PDF) 512 Page - NEC |
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VR4102 Datasheet(HTML) 512 Page - NEC |
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512 / 701 page ![]() CHAPTER 26 FIR (FAST IrDA INTERFACE UNIT) 512 26.2.12 DMACR (0x0C00 0062) Bit D15 D14 D13 D12 D11 D10 D9 D8 Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved R/W RRR RR RR R RTCRST 000 00 00 0 Other resets 0 0 0 0 0 0 0 0 Bit D7D6D5 D4D3 D2D1 D0 Name ACES_MD TRANS_MD Reserved Reserved Reserved DEMAND2 DEMAND1 DEMAND0 R/W R/W R/W R R R R/W R/W R/W RTCRST 000 00 00 0 Other resets 0 0 0 0 0 0 0 0 Bit Name Function D15 to D8 Reserved Write 0 when writing. 0 is returned after a read. D7 ACES_MD This bit is used to select the access mode. Write 0 when writing. 0 is returned after a read. D6 TRANS_MD This bit is used to specify the transfer direction. TRANS_MD Transfer direction 0 1 Memory o TDR RDR o Memory D5 to D3 Reserved Write 0 when writing. 0 is returned after a read. D2 to D0 DEMAND2 to These bits are used to specify the demand size. DEMAND0 DEMAND2 to 0 Demand size 000 001 010 011 100 101 110 1 2 3 4 5 6 7 111 Free size [Caution] During the DMA operation (both the master side and IrDA side), the contents of this register must not be changed. |
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