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VR4102 Datasheet(PDF) 514 Page - NEC

Part # VR4102
Description  64/32-bit Microprocessor
PDF  701 Pages
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Manufacturer  NEC [NEC]
Direct Link  http://www.nec.com/
Logo NEC - NEC

VR4102 Datasheet(HTML) 514 Page - NEC

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CHAPTER 26 FIR (FAST IrDA INTERFACE UNIT)
514
26.2.14 TXIR (0x0C00 0066)
Bit
D15
D14
D13
D12
D11
D10
D9
D8
Name
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
R/W
RRR
RR
RR
R
RTCRST
000
00
00
0
Other resets
0
0
0
0
0
0
0
0
Bit
D7D6D5
D4D3
D2D1
D0
Name
TX_BUSY
Reserved
LAST_TFL
TX_TH_OV
Reserved
TXF_UNDR
TXF_FULL
TXF_EMP
R/W
RRR
RR
RR
R
RTCRST
000
00
00
0
Other resets
0
0
0
0
0
0
0
0
Bit
Name
Function
D15 to D8
Reserved
Write 0 when writing. 0 is returned after a read.
D7
TX_BUSY
Transmission busy.
This bit is set to 1 during the period between PA (in FIR) or STA (in MIR)
transmission and abort transmission.
0: Not Busy
1: Busy
D6
Reserved
Write 0 when writing. 0 is returned after a read.
D5
LAST_TFL
Last transmission frame status.
This bit indicates whether data exists or not in the transmission frame size FIFO.
This bit changes when the STA transmission sequence ends. Its initial value is 1.
0: Normal
1: Exists
D4
TX_TH_OV
Transmission FIFO threshold over status.
This bit indicates whether or not the data size within the transmission FIFO
exceeds the threshold.
0: Normal
1: Excesses
D3
Reserved
Write 0 when writing. 0 is returned after a read.
D2
TXF_UNDR
Transmission FIFO underrun status.
This bit indicates whether or not data is read when there is no data in the
transmission FIFO.
0: Normal
1: Data is read
D1
TXF_FULL
Transmission FIFO full status.
This bit indicates that there is no writable space in the transmission FIFO.
0: Normal
1: No writable space
D0
TXF_EMP
Transmission FIFO empty status.
This bit indicates whether or not data to be read exists in the transmission FIFO.
0: Normal
1: Exists



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