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VR4102 Datasheet(PDF) 521 Page - NEC |
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VR4102 Datasheet(HTML) 521 Page - NEC |
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521 / 701 page  CHAPTER 26 FIR (FAST IrDA INTERFACE UNIT) 521 26.2.18 TXFL (0x0C00 006E) Bit D15 D14 D13 D12 D11 D10 D9 D8 Name Reserved Reserved Reserved TXFL12 TXFL11 TXFL10 TXFL9 TXFL8 R/W R R R R/W R/W R/W R/W R/W RTCRST 000 00 00 0 Other resets 0 0 0 0 0 0 0 0 Bit D7D6D5 D4D3 D2D1 D0 Name TXFL7 TXFL6 TXFL5 TXFL4 TXFL3 TXFL2 TXFL1 TXFL0 R/W R/W R/W R/W R/W R/W R/W R/W R/W RTCRST 000 00 00 0 Other resets 0 0 0 0 0 0 0 0 Bit Name Function D15 to D13 Reserved Write 0 when writing. 0 is returned after a read. D12 to D0 TXFL12 to TXFL0 Transmit frame size. [Function] This register functions as prebuffer address for data write to the transmit frame size data store FIFO, in which data of up to 7 frames can be stored. Setting value = transmit size – 1 Setting range = 1 to 2 Kbytes The FIFO is initialized by setting bit 2 of the FSR register. (1) Write The data transmit size of frames to be transferred is written to this register. Transmission is enabled when data is written to this register in the state other than transmission busy state (after FIFO initialization and after transmission completion). The frames whose number is specified by this register are transferred continuously (back-to-back transfer). During the single frame transfer, FIFO should be initialized at each 1-frame transfer completion to restart transmit operation. (2) Read The sequencer reads the transmission size from this register after the STA flag of transmission frame is transmitted completed. Then, the read pointer is incremented. [Caution] If data exists in the FIFO when the STO transmit sequence is completed, continuous transfer mode is entered. When multiple frames are transferred, be sure to write data to the TXFL register before the STO transmit sequence is completed. |
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