VR4102 datasheet(539/701 Pages) NEC

539 / 701 page

CHAPTER 27 CPU INSTRUCTION SET DETAILS

539

BC0TL

Branch On Coprocessor 0 True Likely

BC0TL

0 1 0 0 0

COPz

0 1 0 0 X X

Note

BCTL

0 0 0 1 1

offset

26 25

21 20

16 15

Format:

BC0TL offset

Description:

A branch target address is computed from the sum of the address of the instruction in the delay slot and the 16-bit

offset, shifted left two bits and sign-extended. If the contents of coprocessor 0’s condition line, as sampled during

the previous instruction, is true, the target address is branched to with a delay of one instruction.

If the conditional branch is not taken, the instruction in the branch delay slot is nullified.

Because the condition line is sampled during the previous instruction, there must be at least one instruction

between this instruction and a coprocessor instruction that changes the condition line.

Operation:

T-1:

condition <- SR18

target <- (offset15)

14 || offset || 02

T+1: if condition then

PC <- PC + target

else

NullifyCurrentInstruction

endif

T-1:

condition <- SR18

target <- (offset15)

46 || offset || 02

T+1: if condition then

PC <- PC + target

else

NullifyCurrentInstruction

endif

Exceptions:

Coprocessor unusable exception

Note

See the opcode table below, or 27.6 CPU INSTRUCTION OPCODE BIT ENCODING.

Opcode Table:

BC0TL

Opcode

Coprocessor

number

BC sub-opcode

Branch condition

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