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VR4102 Datasheet(PDF) 543 Page - NEC

Part # VR4102
Description  64/32-bit Microprocessor
PDF  701 Pages
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Manufacturer  NEC [NEC]
Direct Link  http://www.nec.com/
Logo NEC - NEC

VR4102 Datasheet(HTML) 543 Page - NEC

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CHAPTER 27 CPU INSTRUCTION SET DETAILS
543
BGEZAL Branch On Greater Than Or Equal To Zero And Link BGEZAL
rs
REGIMM
0 0 0 0 0 1
BGEZAL
1 0 0 0 1
offset
31
26 25
21 20
16 15
0
65
5
16
Format:
BGEZAL rs, offset
Description:
A branch target address is computed from the sum of the address of the instruction in the delay slot and the 16-bit
offset, shifted left two bits and sign-extended. Unconditionally, the address of the instruction after the delay slot is
placed in the link register,
r31. If the contents of general register rs have the sign bit cleared, then the program
branches to the target address, with a delay of one instruction.
General register
rs may not be general register r31, because such an instruction is not restartable. An attempt to
execute this instruction is not trapped, however.
Operation:
32
T:
target <- (offset15)
14 || offset || 02
condition <- (GPR [rs]31 = 0)
GPR [31] <- PC + 8
T+1: if condition then
PC <- PC + target
endif
64
T:
target <- (offset15)
46 || offset || 02
condition <- (GPR [rs]63 = 0)
GPR [31] <- PC + 8
T+1: if condition then
PC <- PC + target
endif
Exceptions:
None



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