VR4102 datasheet(544/701 Pages) NEC

544 / 701 page

CHAPTER 27 CPU INSTRUCTION SET DETAILS

544

BGEZALL Branch On Greater Than Or Equal To Zero And Link LikelyBGEZALL

REGIMM

0 0 0 0 0 1

BGEZALL

1 0 0 1 1

offset

26 25

21 20

16 15

Format:

BGEZALL rs, offset

Description:

A branch target address is computed from the sum of the address of the instruction in the delay slot and the 16-bit

offset, shifted left two bits and sign-extended. Unconditionally, the address of the instruction after the delay slot is

placed in the link register,

r31. If the contents of general register rs have the sign bit cleared, then the program

branches to the target address, with a delay of one instruction. General register

rs may not be general register

31, because such an instruction is not restartable. An attempt to execute this instruction is not trapped, however.

If the conditional branch is not taken, the instruction in the branch delay slot is nullified.

Operation:

target <- (offset15)

14 || offset || 02

condition <- (GPR [rs]31 = 0)

GPR [31] <- PC + 8

T+1: if condition then

PC <- PC + target

else

NullifyCurrentInstruction

endif

target <- (offset15)

46 || offset || 02

condition <- (GPR [rs]63 = 0)

GPR [31] <- PC + 8

T+1: if condition then

PC <- PC + target

else

NullifyCurrentInstruction

endif

Exceptions:

None

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