VR4102 datasheet(547/701 Pages) NEC

547 / 701 page

CHAPTER 27 CPU INSTRUCTION SET DETAILS

547

BGTZL

Branch On Greater Than Zero Likely

BGTZL

0 1 0 1 1 1

0 0 0 0 0

offset

26 25

21 20

16 15

Format:

BGTZL rs, offset

Description:

A branch target address is computed from the sum of the address of the instruction in the delay slot and the 16-bit

offset, shifted left two bits and sign-extended. The contents of general register rs are compared to zero. If the

contents of general register

rs have the sign bit cleared and are not equal to zero, then the program branches to

the target address, with a delay of one instruction. If the conditional branch is not taken, the instruction in the

branch delay slot is nullified.

Operation:

target <- (offset15)

14 || offset || 02

condition <- (GPR [rs]31 = 0) and (GPR [rs]

z 0

32)

T+1: if condition then

PC <- PC + target

else

NullifyCurrentInstruction

endif

target <- (offset15)

46 || offset || 02

condition <- (GPR [rs]63 = 0) and (GPR [rs]

z 0

64)

T+1: if condition then

PC <- PC + target

else

NullifyCurrentInstruction

endif

Exceptions:

None

VR4102 Datasheet(PDF) 547 Page - NEC

VR4102 Datasheet(HTML) 547 Page - NEC

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL