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VR4102 Datasheet(PDF) 546 Page - NEC |
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VR4102 Datasheet(HTML) 546 Page - NEC |
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546 / 701 page  CHAPTER 27 CPU INSTRUCTION SET DETAILS 546 BGTZ Branch On Greater Than Zero BGTZ rs BGTZ 0 0 0 1 1 1 0 0 0 0 0 0 offset 31 26 25 21 20 16 15 0 65 5 16 Format: BGTZ rs, offset Description: A branch target address is computed from the sum of the address of the instruction in the delay slot and the 16-bit offset, shifted left two bits and sign-extended. The contents of general register rs are compared to zero. If the contents of general register rs have the sign bit cleared and are not equal to zero, then the program branches to the target address, with a delay of one instruction. Operation: 32 T: target <- (offset15) 14 || offset || 02 condition <- (GPR [rs]31 = 0) and (GPR [rs] z 0 32) T+1: if condition then PC <- PC + target endif 64 T: target <- (offset15) 46 || offset || 02 condition <- (GPR [rs]63 = 0) and (GPR [rs] z 0 64) T+1: if condition then PC <- PC + target endif Exceptions: None |
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