VR4102 datasheet(107/701 Pages) NEC

107 / 701 page

CHAPTER 4 VR4102 PIPELINE

107

(5) Load Word instruction (LW rt, offset (base))

IF stage

Same as the IF stage for the ADD instruction.

RF stage

Same as the RF stage for the ADD instruction. Note that the base field is in the same position as

the rs field.

EX stage

Refer to the EX stage for the ADD instruction.

For LW, the inputs to the ALU come from

GPR[base] through the bypass multiplexer and from the sign-extended offset field. The result of

the ALU operation that is latched into the ALU output latch in

)1 represents the effective virtual

address of the operand (DVA).

DC stage

The cache tag field is compared with the Page Frame Number (PFN) field of the TLB entry. After

passing through the load aligner, aligned data is placed in the DC output latch during

)2.

WB stage

During

)1, the cache read data is written into the register file addressed by the rt field.

Figure 4-9. LW Instruction Pipeline Activities

IF1

Cycle

Phase

PCycle

PClock

IF2

RF1

RF2

EX1

EX2

DC1

DC2

WB1

WB2

ITLB

IDC

ITC

ICA

IDEC

DVA

DCA

DLA

DTLB

DTC

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