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VR4102 Datasheet(PDF) 105 Page - NEC |
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VR4102 Datasheet(HTML) 105 Page - NEC |
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105 / 701 page  CHAPTER 4 VR4102 PIPELINE 105 (3) Branch on Equal instruction (BEQ rs, rt, offset) IF stage Same as the IF stage for the ADD instruction. RF stage During )2, the register file is addressed with the rs and rt fields. A check is performed to determine if each corresponding bit position of these two operands has equal values. If they are equal, the PC is set to PC + target, where target is the sign-extended offset field. If they are not equal, the PC is set to PC + 4. EX stage The next PC resulting from the branch comparison is valid at the beginning of )2 for instruction fetch. DC stage This stage is a NOP for this instruction. WB stage This stage is a NOP for this instruction. Figure 4-7. BEQ Instruction Pipeline Activities IF1 Cycle Phase PCycle PClock IF2 )2 )1 )2 )1 )2 )1 )2 )1 )2 )1 RF1 RF2 EX1 EX2 DC1 DC2 WB1 WB2 ITLB IDC ITC ICA IDEC EX BAC RF |
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